Lines Matching refs:PROCESSOR_ALL
536 { "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL },
539 { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL },
555 { "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL },
556 { "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2, PROCESSOR_ALL },
557 { "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2, PROCESSOR_ALL },
558 { "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2, PROCESSOR_ALL },
568 { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1, PROCESSOR_ALL },
569 { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL },
570 { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL },
573 { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL },
574 { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL },
575 { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL },
592 { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL },
605 { "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
607 { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL },
608 { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
610 { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
611 { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
612 { "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
613 { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL },
614 { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL },
615 { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL },
616 { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL },
617 { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL },
618 { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
619 { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
620 { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
621 { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL },
622 { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL },
625 { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
626 { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
627 { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
628 { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
629 { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
632 { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL },
633 { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL },
634 { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL },
635 { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL },
636 { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL },
637 { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL },
638 { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL },
639 { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL },
640 { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
641 { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
642 { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
643 { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
644 { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
645 { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
650 { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
651 { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
652 { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
653 { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
655 { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
656 { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
657 { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
658 { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
660 { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
661 { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
663 { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
664 { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
665 { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
666 { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
667 { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
668 { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
669 { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
670 { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
671 { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
672 { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL },
680 { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
681 { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
682 { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
683 { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
685 { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
686 { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
687 { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
688 { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
690 { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
691 { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
693 { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
694 { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
695 { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
696 { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
697 { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
698 { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
699 { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
700 { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
701 { "jsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL },
702 { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
704 { "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL },
705 { "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL },
708 { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
710 { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
712 { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
714 { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
718 { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
719 { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
720 { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
721 { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
722 { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL },
723 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL },
724 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL },