Lines Matching refs:vs
8391 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_PH2_MATCH_PRESETS_BB (0x1<<31) // Enable preset vs ceofficient matching during Phase 2 based on Serdes request
8428 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYLINKUP_HOLDOFF_BB (0x1<<21) // Enable PhyLinkUp holdoff in Gen3 (for InitFC vs UpdateFC issue)