Lines Matching defs:op2
94 void add32(RegisterID op1, RegisterID op2, RegisterID dest)
96 m_assembler.adds(dest, op1, op2);
134 void and32(RegisterID op1, RegisterID op2, RegisterID dest)
136 m_assembler.bitAnds(dest, op1, op2);
186 void mul32(RegisterID op1, RegisterID op2, RegisterID dest)
188 if (op2 == dest) {
190 move(op2, ARMRegisters::S0);
191 op2 = ARMRegisters::S0;
195 op1 = op2;
196 op2 = tmp;
199 m_assembler.muls(dest, op1, op2);
241 void or32(RegisterID op1, RegisterID op2, RegisterID dest)
243 m_assembler.orrs(dest, op1, op2);
325 void xor32(RegisterID op1, RegisterID op2, RegisterID dest)
327 m_assembler.eors(dest, op1, op2);
757 Jump branchAdd32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
761 add32(op1, op2, dest);
794 void mull32(RegisterID op1, RegisterID op2, RegisterID dest)
796 if (op2 == dest) {
798 move(op2, ARMRegisters::S0);
799 op2 = ARMRegisters::S0;
803 op1 = op2;
804 op2 = tmp;
807 m_assembler.mull(ARMRegisters::S1, dest, op1, op2);
862 Jump branchSub32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
865 m_assembler.subs(dest, op1, op2);
1174 void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
1176 m_assembler.vadd_f64(dest, op1, op2);
1196 void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
1198 m_assembler.vdiv_f64(dest, op1, op2);
1213 void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
1215 m_assembler.vsub_f64(dest, op1, op2);
1235 void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
1237 m_assembler.vmul_f64(dest, op1, op2);