Lines Matching refs:zr
431 zr = 0x3f,
473 static bool isZr(RegisterID reg) { return reg == zr; }
1137 add<datasize, S>(ARM64Registers::zr, rn, imm12, shift);
1143 add<datasize, S>(ARM64Registers::zr, rn, rm);
1149 add<datasize, S>(ARM64Registers::zr, rn, rm, extend, amount);
1155 add<datasize, S>(ARM64Registers::zr, rn, rm, shift, amount);
1161 sub<datasize, S>(ARM64Registers::zr, rn, imm12, shift);
1167 sub<datasize, S>(ARM64Registers::zr, rn, rm);
1173 sub<datasize, S>(ARM64Registers::zr, rn, rm, extend, amount);
1179 sub<datasize, S>(ARM64Registers::zr, rn, rm, shift, amount);
1198 csinc<datasize>(rd, ARM64Registers::zr, ARM64Registers::zr, invert(cond));
1204 csinv<datasize>(rd, ARM64Registers::zr, ARM64Registers::zr, invert(cond));
1577 msub<datasize>(rd, rn, rm, ARM64Registers::zr);
1586 orr<datasize>(rd, ARM64Registers::zr, rm);
1592 orr<datasize>(rd, ARM64Registers::zr, imm);
1629 madd<datasize>(rd, rn, rm, ARM64Registers::zr);
1635 orn<datasize>(rd, ARM64Registers::zr, rm);
1641 orn<datasize>(rd, ARM64Registers::zr, rm, shift, amount);
1647 sub<datasize, setFlags>(rd, ARM64Registers::zr, rm);
1653 sub<datasize, setFlags>(rd, ARM64Registers::zr, rm, shift, amount);
1659 sbc<datasize, setFlags>(rd, ARM64Registers::zr, rm);
1665 sbc<datasize, setFlags>(rd, ARM64Registers::zr, rm, shift, amount);
1814 smsubl(rd, rn, rm, ARM64Registers::zr);
1824 insn(dataProcessing3Source(Datasize_64, DataOp_SMULH, rm, ARM64Registers::zr, rn, rd));
1829 smaddl(rd, rn, rm, ARM64Registers::zr);
2017 and_<datasize, S>(ARM64Registers::zr, rn, rm);
2023 and_<datasize, S>(ARM64Registers::zr, rn, rm, shift, amount);
2029 and_<datasize, S>(ARM64Registers::zr, rn, imm);
2065 umsubl(rd, rn, rm, ARM64Registers::zr);
2075 insn(dataProcessing3Source(Datasize_64, DataOp_UMULH, rm, ARM64Registers::zr, rn, rd));
2080 umaddl(rd, rn, rm, ARM64Registers::zr);
3162 static RegisterID disassembleXOrZr(int reg) { return reg == 31 ? ARM64Registers::zr : static_cast<RegisterID>(reg); }
3163 static RegisterID disassembleXOrZrOrSp(bool useZr, int reg) { return reg == 31 ? (useZr ? ARM64Registers::zr : ARM64Registers::sp) : static_cast<RegisterID>(reg); }
3603 return system(0, 0, 3, 2, (imm >> 3) & 0xf, imm & 0x7, ARM64Registers::zr);