powerpc/copyloops/memcpy_power7.S

38 	neg	r6,r4
43 	lbz	r0,0(r4)
44 	addi	r4,r4,1
49 	lhz	r0,0(r4)
50 	addi	r4,r4,2
55 	lwz	r0,0(r4)
56 	addi	r4,r4,4
83 	ld	r0,0(r4)
84 	ld	r6,8(r4)
85 	ld	r7,16(r4)
86 	ld	r8,24(r4)
87 	ld	r9,32(r4)
88 	ld	r10,40(r4)
89 	ld	r11,48(r4)
90 	ld	r12,56(r4)
91 	ld	r14,64(r4)
92 	ld	r15,72(r4)
93 	ld	r16,80(r4)
94 	ld	r17,88(r4)
95 	ld	r18,96(r4)
96 	ld	r19,104(r4)
97 	ld	r20,112(r4)
98 	ld	r21,120(r4)
99 	addi	r4,r4,128
137 	ld	r0,0(r4)
138 	ld	r6,8(r4)
139 	ld	r7,16(r4)
140 	ld	r8,24(r4)
141 	ld	r9,32(r4)
142 	ld	r10,40(r4)
143 	ld	r11,48(r4)
144 	ld	r12,56(r4)
145 	addi	r4,r4,64
158 	ld	r0,0(r4)
159 	ld	r6,8(r4)
160 	ld	r7,16(r4)
161 	ld	r8,24(r4)
162 	addi	r4,r4,32
171 	ld	r0,0(r4)
172 	ld	r6,8(r4)
173 	addi	r4,r4,16
184 	lwz	r0,0(r4)	/* Less chance of a reject with word ops */
185 	lwz	r6,4(r4)
186 	addi	r4,r4,8
192 	lwz	r0,0(r4)
193 	addi	r4,r4,4
198 	lhz	r0,0(r4)
199 	addi	r4,r4,2
204 	lbz	r0,0(r4)
217 	std	r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
225 	ld	r4,STK_REG(R30)(r1)
234 	clrrdi	r6,r4,7
255 	xor	r6,r4,r3
265 	lbz	r0,0(r4)
266 	addi	r4,r4,1
271 	lhz	r0,0(r4)
272 	addi	r4,r4,2
277 	lwz	r0,0(r4)
278 	addi	r4,r4,4
283 	ld	r0,0(r4)
284 	addi	r4,r4,8
301 	lvx	v1,0,r4
302 	addi	r4,r4,16
307 	lvx	v1,0,r4
308 	lvx	v0,r4,r9
309 	addi	r4,r4,32
315 	lvx	v3,0,r4
316 	lvx	v2,r4,r9
317 	lvx	v1,r4,r10
318 	lvx	v0,r4,r11
319 	addi	r4,r4,64
346 	lvx	v7,0,r4
347 	lvx	v6,r4,r9
348 	lvx	v5,r4,r10
349 	lvx	v4,r4,r11
350 	lvx	v3,r4,r12
351 	lvx	v2,r4,r14
352 	lvx	v1,r4,r15
353 	lvx	v0,r4,r16
354 	addi	r4,r4,128
376 	lvx	v3,0,r4
377 	lvx	v2,r4,r9
378 	lvx	v1,r4,r10
379 	lvx	v0,r4,r11
380 	addi	r4,r4,64
388 	lvx	v1,0,r4
389 	lvx	v0,r4,r9
390 	addi	r4,r4,32
396 	lvx	v1,0,r4
397 	addi	r4,r4,16
405 	ld	r0,0(r4)
406 	addi	r4,r4,8
411 	lwz	r0,0(r4)
412 	addi	r4,r4,4
417 	lhz	r0,0(r4)
418 	addi	r4,r4,2
423 	lbz	r0,0(r4)
437 	lbz	r0,0(r4)
438 	addi	r4,r4,1
443 	lhz	r0,0(r4)
444 	addi	r4,r4,2
449 	lwz	r0,0(r4)
450 	addi	r4,r4,4
455 	lwz	r0,0(r4)	/* Less chance of a reject with word ops */
456 	lwz	r7,4(r4)
457 	addi	r4,r4,8
474 	LVS(v16,0,r4)		/* Setup permute control vector */
475 	lvx	v0,0,r4
476 	addi	r4,r4,16
479 	lvx	v1,0,r4
481 	addi	r4,r4,16
487 	lvx	v1,0,r4
489 	lvx	v0,r4,r9
491 	addi	r4,r4,32
497 	lvx	v3,0,r4
499 	lvx	v2,r4,r9
501 	lvx	v1,r4,r10
503 	lvx	v0,r4,r11
505 	addi	r4,r4,64
532 	lvx	v7,0,r4
534 	lvx	v6,r4,r9
536 	lvx	v5,r4,r10
538 	lvx	v4,r4,r11
540 	lvx	v3,r4,r12
542 	lvx	v2,r4,r14
544 	lvx	v1,r4,r15
546 	lvx	v0,r4,r16
548 	addi	r4,r4,128
570 	lvx	v3,0,r4
572 	lvx	v2,r4,r9
574 	lvx	v1,r4,r10
576 	lvx	v0,r4,r11
578 	addi	r4,r4,64
586 	lvx	v1,0,r4
588 	lvx	v0,r4,r9
590 	addi	r4,r4,32
596 	lvx	v1,0,r4
598 	addi	r4,r4,16
604 	addi	r4,r4,-16	/* Unwind the +16 load offset */
607 	lwz	r0,0(r4)	/* Less chance of a reject with word ops */
608 	lwz	r6,4(r4)
609 	addi	r4,r4,8
615 	lwz	r0,0(r4)
616 	addi	r4,r4,4
621 	lhz	r0,0(r4)
622 	addi	r4,r4,2
627 	lbz	r0,0(r4)