Lines Matching refs:wrmsr
85 wrmsr(msr, v);
90 wrmsr(msr, v);
114 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
115 wrmsr(MSR_P6_EVNTSEL0, ARCH_PERFMON_EVENTSEL_ENABLE |
117 wrmsr(MSR_P6_EVNTSEL1, ARCH_PERFMON_EVENTSEL_ENABLE |
119 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0x3);
138 wrmsr(MSR_K7_EVNTSEL0, 0);
139 wrmsr(MSR_K7_EVNTSEL0, ARCH_PERFMON_EVENTSEL_ENABLE |
141 wrmsr(MSR_K7_EVNTSEL1, ARCH_PERFMON_EVENTSEL_ENABLE |
471 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
473 wrmsr(MSR_P6_EVNTSEL0 + 0, ARCH_PERFMON_EVENTSEL_ENABLE |
475 wrmsr(MSR_P6_EVNTSEL0 + 1, ARCH_PERFMON_EVENTSEL_ENABLE |
477 wrmsr(MSR_P6_EVNTSEL0 + 2, ARCH_PERFMON_EVENTSEL_ENABLE |
480 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0x7);
490 wrmsr(MSR_K7_EVNTSEL0, 0);
491 wrmsr(MSR_K7_EVNTSEL1, 0);
492 wrmsr(MSR_K7_EVNTSEL2, 0);
494 wrmsr(MSR_K7_EVNTSEL0, ARCH_PERFMON_EVENTSEL_ENABLE |
496 wrmsr(MSR_K7_EVNTSEL1, ARCH_PERFMON_EVENTSEL_ENABLE |
498 wrmsr(MSR_K7_EVNTSEL2, ARCH_PERFMON_EVENTSEL_ENABLE |
763 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
764 wrmsr(MSR_CORE_PERF_FIXED_CTR0 + idx, 0);
767 wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(idx, FIXED_PMC_KERNEL));
768 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, FIXED_PMC_GLOBAL_CTRL_ENABLE(idx));
770 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);