Lines Matching refs:exception
22 * Bit '0' is set on Intel if the exception occurs while delivering a previous
23 * event/exception. AMD's wording is ambiguous, but presumably the bit is set
24 * if the exception occurs while delivering an external event, e.g. NMI or INTR,
141 * VMX disallows injecting an exception with error_code[31:16] != 0,
196 TEST_ASSERT(!events.exception.pending,
197 "Vector %d unexpectedlt pending", events.exception.nr);
198 TEST_ASSERT(!events.exception.injected,
199 "Vector %d unexpectedly injected", events.exception.nr);
202 events.exception.pending = !inject;
203 events.exception.injected = inject;
204 events.exception.nr = SS_VECTOR;
205 events.exception.has_error_code = true;
206 events.exception.error_code = SS_ERROR_CODE;
212 * when an exception is being queued for L2. Specifically, verify that KVM
213 * honors L1 exception intercept controls when a #SS is pending/injected,
250 TEST_ASSERT_EQ(events.exception.pending, true);
251 TEST_ASSERT_EQ(events.exception.nr, SS_VECTOR);
252 TEST_ASSERT_EQ(events.exception.has_error_code, true);
253 TEST_ASSERT_EQ(events.exception.error_code, SS_ERROR_CODE);