x86/turbostat/turbostat.c

301 int get_msr(int cpu, off_t offset, unsigned long long *msr);
357 	if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
1257 	/* get_msr_sum() = sum + (get_msr() - last) */
1590 int get_msr(int cpu, off_t offset, unsigned long long *msr)
2977 		if (get_msr(cpu, mp->msr_num, counterp))
3029 	get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
3313 	if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
3321 	if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
3326 	if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
3421 				if (get_msr(cpu, rci->msr[i], &rci->data[i]))
3498 		if (get_msr(cpu, MSR_SMI_COUNT, &msr))
3503 		if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
3523 		if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
3528 		if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
3531 		if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
3536 		if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
3550 		if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
3554 		if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
3572 		if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
3576 		if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
3580 		if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
3584 		if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
3588 		if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
3592 			if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
3595 			if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
3601 		if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
3604 		if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
3607 		if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
3610 		if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
3613 		if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
3628 		if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
3778 	get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
3790 	get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
3808 	get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
3824 	get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
3843 	get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
3886 	get_msr(base_cpu, trl_msr_offset, &msr);
3891 		get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
3915 	get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
3930 	get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
3960 	get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
4014 	get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
4039 	get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
4043 	get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
4053 	get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
4063 	get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
4070 	get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
4087 		get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
4094 		get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
4101 		get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
4108 		get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
4115 		get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
4122 		get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
4899 	/* get_msr_sum() = sum + (get_msr() - last) */
4900 	ret = get_msr(cpu, offset, &msr_cur);
4932 		ret = get_msr(cpu, offset, &msr_cur);
5207 	get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
5666 	if (get_msr(cpu, MSR_PM_ENABLE, &msr))
5675 	if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
5685 	if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
5698 		if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
5710 		if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
5717 	if (get_msr(cpu, MSR_HWP_STATUS, &msr))
5753 		get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
5786 		get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
5806 		get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
5840 		if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
5869 	if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
5908 	if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr))
5958 		if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr))
5962 		if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
5971 		if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
5984 		if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
5998 		if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr))
6007 		if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
6018 		if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
6026 		if (get_msr(cpu, MSR_PP0_POLICY, &msr))
6032 		if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
6039 		if (get_msr(cpu, MSR_PP1_POLICY, &msr))
6044 		if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
6119 	if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
6128 		if (bits && !get_msr(base_cpu, MSR_PLATFORM_INFO, &enabled))
6181 		if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
6187 		if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
6199 		if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
6207 		if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
6266 	if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr))
6281 	if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
6301 	if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
6325 	if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
6347 	if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
6351 	if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
6766 		if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch))
6767 			warnx("get_msr(UCODE)");