perf/util/amd-sample-raw.c

23 static void pr_ibs_fetch_ctl(union ibs_fetch_ctl reg)
50 		if (reg.phy_addr_valid)
51 			l1tlb_pgsz_str = l1tlb_pgsz_strs_erratum1347[reg.l1tlb_pgsz];
53 		if (reg.phy_addr_valid)
54 			l1tlb_pgsz_str = l1tlb_pgsz_strs[reg.l1tlb_pgsz];
55 		ic_miss_str = ic_miss_strs[reg.ic_miss];
61 			 reg.l3_miss_only, reg.fetch_oc_miss, reg.fetch_l3_miss);
66 		reg.val, reg.fetch_maxcnt << 4, reg.fetch_cnt << 4, reg.fetch_lat,
67 		reg.fetch_en, reg.fetch_val, reg.fetch_comp, ic_miss_str ? : "",
68 		reg.phy_addr_valid, l1tlb_pgsz_str ? : "", reg.l1tlb_miss, reg.l2tlb_miss,
69 		reg.rand_en, reg.fetch_comp ? (reg.fetch_l2_miss ? " L2Miss 1" : " L2Miss 0") : "",
73 static void pr_ic_ibs_extd_ctl(union ic_ibs_extd_ctl reg)
75 	printf("ic_ibs_ext_ctl:\t%016llx IbsItlbRefillLat %3d\n", reg.val, reg.itlb_refill_lat);
78 static void pr_ibs_op_ctl(union ibs_op_ctl reg)
83 		snprintf(l3_miss_only, sizeof(l3_miss_only), " L3MissOnly %d", reg.l3_miss_only);
86 		reg.val, ((reg.opmaxcnt_ext << 16) | reg.opmaxcnt) << 4, l3_miss_only,
87 		reg.op_en, reg.op_val, reg.cnt_ctl,
88 		reg.cnt_ctl ? "uOps" : "cycles", reg.opcurcnt);
91 static void pr_ibs_op_data(union ibs_op_data reg)
95 		reg.val, reg.comp_to_ret_ctr, reg.tag_to_ret_ctr,
96 		reg.op_brn_ret ? (reg.op_return ? " OpReturn 1" : " OpReturn 0") : "",
97 		reg.op_brn_ret ? (reg.op_brn_taken ? " OpBrnTaken 1" : " OpBrnTaken 0") : "",
98 		reg.op_brn_ret ? (reg.op_brn_misp ? " OpBrnMisp 1" : " OpBrnMisp 0") : "",
99 		reg.op_brn_ret, reg.op_rip_invalid, reg.op_brn_fuse, reg.op_microcode);
102 static void pr_ibs_op_data2_extended(union ibs_op_data2 reg)
120 	int data_src = (reg.data_src_hi << 3) | reg.data_src_lo;
122 	printf("ibs_op_data2:\t%016llx %sRmtNode %d%s\n", reg.val,
124 			(reg.cache_hit_st ? "CacheHitSt 1=O-State " : "CacheHitSt 0=M-state ") : "",
125 		reg.rmt_node,
129 static void pr_ibs_op_data2_default(union ibs_op_data2 reg)
142 	printf("ibs_op_data2:\t%016llx %sRmtNode %d%s\n", reg.val,
143 	       reg.data_src_lo == 2 ? (reg.cache_hit_st ? "CacheHitSt 1=O-State "
145 	       reg.rmt_node, data_src_str[reg.data_src_lo]);
148 static void pr_ibs_op_data2(union ibs_op_data2 reg)
151 		return pr_ibs_op_data2_extended(reg);
152 	pr_ibs_op_data2_default(reg);
155 static void pr_ibs_op_data3(union ibs_op_data3 reg)
165 	if (!(cpu_family == 0x19 && cpu_model < 0x10 && (reg.dc_miss_no_mab_alloc || reg.sw_pf))) {
166 		snprintf(l2_miss_str, sizeof(l2_miss_str), " L2Miss %d", reg.l2_miss);
168 			 " OpDcMissOpenMemReqs %2d", reg.op_dc_miss_open_mem_reqs);
171 	if (reg.op_mem_width)
173 			 " OpMemWidth %2d bytes", 1 << (reg.op_mem_width - 1));
179 		reg.val, reg.ld_op, reg.st_op, reg.dc_l1tlb_miss, reg.dc_l2tlb_miss,
180 		reg.dc_l1tlb_hit_2m, reg.dc_l1tlb_hit_1g, reg.dc_l2tlb_hit_2m, reg.dc_miss,
181 		reg.dc_mis_acc, reg.dc_wc_mem_acc, reg.dc_uc_mem_acc, reg.dc_locked_op,
182 		reg.dc_miss_no_mab_alloc, reg.dc_lin_addr_valid, reg.dc_phy_addr_valid,
183 		reg.dc_l2_tlb_hit_1g, l2_miss_str, reg.sw_pf, op_mem_width_str,
184 		op_dc_miss_open_mem_reqs_str, reg.dc_miss_lat, reg.tlb_refill_lat);