Lines Matching refs:desc
18 .desc = "L3 cache access, read",
25 .desc = "Number of segment register loads",
31 .desc = "Memory cluster signals to block micro-op dispatch for any reason",
37 .desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
43 .desc = "DDRC write commands. Unit: hisi_sccl,ddrc ",
51 .desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: uncore_cbox ",
59 .desc = "UNC_CBO_HYPHEN. Unit: uncore_cbox ",
67 .desc = "UNC_CBO_TWO_HYPH. Unit: uncore_cbox ",
75 .desc = "Total read hits. Unit: hisi_sccl,l3c ",
83 .desc = "Total cache misses. Unit: uncore_imc_free_running ",
91 .desc = "Total cache hits. Unit: uncore_imc ",
99 .desc = "L1 BTB Correction",
105 .desc = "L2 BTB Correction",
111 .desc = 0,
234 .desc = "ddr write-cycles event. Unit: uncore_sys_ddr_pmu ",
242 .desc = "ccn read-cycles event. Unit: uncore_sys_ccn_pmu ",
250 .desc = "Counts total cache misses in first lookup result (high priority). Unit: uncore_sys_cmn_pmu ",
258 .desc = 0,