Lines Matching refs:mcasp
40 #include "davinci-mcasp.h"
71 struct davinci_mcasp *mcasp;
131 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
134 void __iomem *reg = mcasp->base + offset;
138 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
141 void __iomem *reg = mcasp->base + offset;
145 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
148 void __iomem *reg = mcasp->base + offset;
152 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
155 __raw_writel(val, mcasp->base + offset);
158 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
160 return (u32)__raw_readl(mcasp->base + offset);
163 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
167 mcasp_set_bits(mcasp, ctl_reg, val);
172 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
176 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
180 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
182 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
183 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
188 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
192 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
194 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
196 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
200 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
204 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
206 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
208 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
212 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
214 if (mcasp->rxnumevt) { /* enable FIFO */
215 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
217 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
218 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
229 if (mcasp_is_synchronous(mcasp)) {
230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
232 mcasp_set_clk_pdir(mcasp, true);
236 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
237 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
239 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
241 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
242 if (mcasp_is_synchronous(mcasp))
243 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
246 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
247 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
250 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
254 if (mcasp->txnumevt) { /* enable FIFO */
255 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
257 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
258 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
262 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
263 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
264 mcasp_set_clk_pdir(mcasp, true);
267 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
268 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
272 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
276 mcasp_set_axr_pdir(mcasp, true);
279 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
281 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
284 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
285 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
288 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
290 mcasp->streams++;
293 mcasp_start_tx(mcasp);
295 mcasp_start_rx(mcasp);
298 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
301 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
302 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
308 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
309 mcasp_set_clk_pdir(mcasp, false);
310 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
313 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
314 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
316 if (mcasp->rxnumevt) { /* disable FIFO */
317 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
319 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
323 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
328 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
329 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
335 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
338 mcasp_set_clk_pdir(mcasp, false);
341 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
342 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
344 if (mcasp->txnumevt) { /* disable FIFO */
345 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
347 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
350 mcasp_set_axr_pdir(mcasp, false);
353 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
355 mcasp->streams--;
358 mcasp_stop_tx(mcasp);
360 mcasp_stop_rx(mcasp);
365 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
367 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
371 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
373 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
376 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
382 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
389 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
396 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
398 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
402 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
404 dev_warn(mcasp->dev, "Receive buffer overflow\n");
407 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
413 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
420 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
427 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
430 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
433 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
442 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
451 pm_runtime_get_sync(mcasp->dev);
454 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
455 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
461 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
468 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
469 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
478 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
479 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
488 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
490 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
496 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
497 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
499 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
500 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
503 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
504 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
506 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
507 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
509 mcasp->bclk_master = 1;
513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
516 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
517 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
520 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
521 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
523 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
524 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
526 mcasp->bclk_master = 1;
530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
531 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
533 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
534 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
537 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
538 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
540 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
541 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
543 mcasp->bclk_master = 0;
547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
550 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
551 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
554 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
555 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
557 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
558 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
560 mcasp->bclk_master = 0;
569 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
570 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
574 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
575 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
579 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
580 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
584 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
585 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
597 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
598 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
600 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
601 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
604 mcasp->dai_fmt = fmt;
606 pm_runtime_put(mcasp->dev);
610 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
613 pm_runtime_get_sync(mcasp->dev);
616 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
618 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
623 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
625 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
628 mcasp->bclk_div = div;
642 mcasp->slot_width = div / mcasp->tdm_slots;
643 if (div % mcasp->tdm_slots)
644 dev_warn(mcasp->dev,
646 __func__, div, mcasp->tdm_slots);
653 pm_runtime_put(mcasp->dev);
660 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
662 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
668 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
670 pm_runtime_get_sync(mcasp->dev);
675 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
677 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
679 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
682 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
684 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
686 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
689 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
694 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
695 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
696 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
702 mcasp->sysclk_freq = freq;
704 pm_runtime_put(mcasp->dev);
709 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
712 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
714 int slots = mcasp->tdm_slots;
717 if (mcasp->tdm_mask[stream])
718 slots = hweight32(mcasp->tdm_mask[stream]);
731 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
735 for (i = 0; i < mcasp->num_serializer; i++)
736 if (mcasp->serial_dir[i] == TX_MODE)
738 else if (mcasp->serial_dir[i] == RX_MODE)
741 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
746 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
758 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
760 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
763 dev_dbg(mcasp->dev,
768 dev_err(mcasp->dev,
776 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
781 mcasp->tdm_slots = slots;
782 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
783 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
784 mcasp->slot_width = slot_width;
786 return davinci_mcasp_set_ch_constraints(mcasp);
789 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
796 if (mcasp->slot_width)
797 slot_width = mcasp->slot_width;
798 else if (mcasp->max_format_width)
799 slot_width = mcasp->max_format_width;
811 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
823 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
824 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
826 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
828 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
830 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
832 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
843 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
845 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15),
849 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
854 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
857 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
861 u8 slots = mcasp->tdm_slots;
867 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
873 if (mcasp->version < MCASP_VERSION_3)
874 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
877 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
878 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
881 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
883 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
884 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
886 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
890 for (i = 0; i < mcasp->num_serializer; i++) {
891 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
892 mcasp->serial_dir[i]);
893 if (mcasp->serial_dir[i] == TX_MODE &&
895 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
896 mcasp->dismod, DISMOD_MASK);
897 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
899 } else if (mcasp->serial_dir[i] == RX_MODE &&
901 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
905 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
908 if (mcasp->serial_dir[i] != INACTIVE_MODE)
909 mcasp_mod_bits(mcasp,
911 mcasp->dismod, DISMOD_MASK);
912 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
918 numevt = mcasp->txnumevt;
919 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
922 numevt = mcasp->rxnumevt;
923 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
927 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
928 "enabled in mcasp (%d)\n", channels,
952 dev_err(mcasp->dev, "Invalid combination of period words and "
970 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
971 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
979 mcasp->active_serializers[stream] = active_serializers;
984 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
993 total_slots = mcasp->tdm_slots;
1001 if (mcasp->tdm_mask[stream]) {
1002 active_slots = hweight32(mcasp->tdm_mask[stream]);
1007 if ((1 << i) & mcasp->tdm_mask[stream]) {
1024 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
1026 if (!mcasp->dat_port)
1030 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
1031 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
1032 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1035 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
1036 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
1037 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
1044 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
1045 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1053 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1056 u8 *cs_bytes = (u8 *)&mcasp->iec958_status;
1058 if (!mcasp->dat_port)
1059 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);
1061 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);
1064 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1066 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF);
1069 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1072 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1074 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1107 dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate);
1111 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status);
1112 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status);
1115 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1120 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1124 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1140 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1158 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1161 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1163 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1170 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1172 if (!mcasp->txnumevt)
1175 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1178 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1180 if (!mcasp->rxnumevt)
1183 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1190 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1194 fifo_use = davinci_mcasp_tx_delay(mcasp);
1196 fifo_use = davinci_mcasp_rx_delay(mcasp);
1210 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1243 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1247 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1252 * If mcasp is BCLK master, and a BCLK divider was not provided by
1255 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1256 int slots = mcasp->tdm_slots;
1261 if (mcasp->slot_width)
1262 sbits = mcasp->slot_width;
1264 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1269 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1273 ret = mcasp_common_hw_param(mcasp, substream->stream,
1278 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1279 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1281 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1287 davinci_config_channel_size(mcasp, word_length);
1289 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1290 mcasp->channels = channels;
1291 if (!mcasp->max_format_width)
1292 mcasp->max_format_width = word_length;
1301 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1308 davinci_mcasp_start(mcasp, substream->stream);
1313 davinci_mcasp_stop(mcasp, substream->stream);
1333 slot_width = rd->mcasp->slot_width;
1356 format_width = rd->mcasp->max_format_width;
1383 int slots = rd->mcasp->tdm_slots;
1387 if (rd->mcasp->slot_width)
1388 sbits = rd->mcasp->slot_width;
1400 if (rd->mcasp->auxclk_fs_ratio)
1402 rd->mcasp->auxclk_fs_ratio;
1404 sysclk_freq = rd->mcasp->sysclk_freq;
1406 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1418 dev_dbg(rd->mcasp->dev,
1433 int slots = rd->mcasp->tdm_slots;
1445 if (rd->mcasp->auxclk_fs_ratio)
1447 rd->mcasp->auxclk_fs_ratio;
1449 sysclk_freq = rd->mcasp->sysclk_freq;
1451 if (rd->mcasp->slot_width)
1452 sbits = rd->mcasp->slot_width;
1454 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1463 dev_dbg(rd->mcasp->dev,
1487 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1489 &mcasp->ruledata[substream->stream];
1492 int tdm_slots = mcasp->tdm_slots;
1495 if (mcasp->substreams[substream->stream])
1498 mcasp->substreams[substream->stream] = substream;
1500 if (mcasp->tdm_mask[substream->stream])
1501 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1503 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1515 for (i = 0; i < mcasp->num_serializer; i++) {
1516 if (mcasp->serial_dir[i] == dir)
1520 ruledata->mcasp = mcasp;
1529 if (mcasp->channels && mcasp->channels < max_channels &&
1531 max_channels = mcasp->channels;
1545 &mcasp->chconstr[substream->stream]);
1547 if (mcasp->max_format_width) {
1560 else if (mcasp->slot_width) {
1575 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1603 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1605 mcasp->substreams[substream->stream] = NULL;
1606 mcasp->active_serializers[substream->stream] = 0;
1608 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1612 mcasp->channels = 0;
1613 mcasp->max_format_width = 0;
1630 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1632 memcpy(uctl->value.iec958.status, &mcasp->iec958_status,
1633 sizeof(mcasp->iec958_status));
1642 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1644 memcpy(&mcasp->iec958_status, uctl->value.iec958.status,
1645 sizeof(mcasp->iec958_status));
1654 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1656 memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status));
1678 static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp)
1680 unsigned char *cs = (u8 *)&mcasp->iec958_status;
1690 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1694 snd_soc_dai_dma_data_set(dai, stream, &mcasp->dma_data[stream]);
1696 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) {
1697 davinci_mcasp_init_iec958_status(mcasp);
1733 .name = "davinci-mcasp.0",
1753 .name = "davinci-mcasp.1",
1768 .name = "davinci-mcasp",
1806 .compatible = "ti,dm646x-mcasp-audio",
1810 .compatible = "ti,da830-mcasp-audio",
1814 .compatible = "ti,am33xx-mcasp-audio",
1818 .compatible = "ti,dra7-mcasp-audio",
1822 .compatible = "ti,omap4-mcasp-audio",
1871 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp)
1874 return of_property_read_bool(mcasp->dev->of_node, "gpio-controller");
1880 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp,
1908 mcasp->missing_audio_param = true;
1920 mcasp->missing_audio_param = true;
1939 mcasp->missing_audio_param = true;
1950 mcasp->auxclk_fs_ratio = val;
1964 mcasp->pdata = pdata;
1966 if (mcasp->missing_audio_param) {
1967 if (davinci_mcasp_have_gpiochip(mcasp)) {
1976 mcasp->op_mode = pdata->op_mode;
1978 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1982 mcasp->tdm_slots = 2;
1986 mcasp->tdm_slots = 32;
1988 mcasp->tdm_slots = pdata->tdm_slots;
1991 mcasp->tdm_slots = 32;
1994 mcasp->num_serializer = pdata->num_serializer;
1996 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1997 mcasp->num_serializer, sizeof(u32),
1999 if (!mcasp->context.xrsr_regs)
2002 mcasp->serial_dir = pdata->serial_dir;
2003 mcasp->version = pdata->version;
2004 mcasp->txnumevt = pdata->txnumevt;
2005 mcasp->rxnumevt = pdata->rxnumevt;
2006 mcasp->dismod = pdata->dismod;
2018 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
2024 if (!mcasp->dev->of_node)
2027 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
2028 chan = dma_request_chan(mcasp->dev, tmp);
2030 return dev_err_probe(mcasp->dev, PTR_ERR(chan),
2041 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
2047 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
2107 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2109 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
2110 mcasp->serial_dir[offset] != INACTIVE_MODE) {
2111 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
2116 return pm_runtime_resume_and_get(mcasp->dev);
2121 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2124 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2127 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2129 pm_runtime_put_sync(mcasp->dev);
2135 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2139 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2141 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2143 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2146 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2149 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2158 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2161 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2163 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2169 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2172 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2175 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2178 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2186 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2189 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
2199 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2202 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
2222 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2224 if (!davinci_mcasp_have_gpiochip(mcasp))
2227 mcasp->gpio_chip = davinci_mcasp_template_chip;
2228 mcasp->gpio_chip.label = dev_name(mcasp->dev);
2229 mcasp->gpio_chip.parent = mcasp->dev;
2231 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2235 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2245 struct davinci_mcasp *mcasp;
2255 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2257 if (!mcasp)
2271 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2272 if (IS_ERR(mcasp->base))
2273 return PTR_ERR(mcasp->base);
2275 dev_set_drvdata(&pdev->dev, mcasp);
2278 mcasp->dev = &pdev->dev;
2279 ret = davinci_mcasp_get_config(mcasp, pdev);
2284 pm_runtime_get_sync(mcasp->dev);
2285 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2286 pm_runtime_put(mcasp->dev);
2289 if (mcasp->missing_audio_param)
2303 irq_name, mcasp);
2309 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2310 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2323 IRQF_ONESHOT, irq_name, mcasp);
2329 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2342 IRQF_ONESHOT, irq_name, mcasp);
2348 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2353 mcasp->dat_port = true;
2355 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2363 if (mcasp->version == MCASP_VERSION_OMAP)
2364 dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata);
2366 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata);
2371 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2372 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2378 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata);
2381 if (mcasp->version < MCASP_VERSION_3) {
2382 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2384 mcasp->dat_port = true;
2386 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2396 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2397 devm_kcalloc(mcasp->dev,
2398 32 + mcasp->num_serializer - 1,
2402 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2403 devm_kcalloc(mcasp->dev,
2404 32 + mcasp->num_serializer - 1,
2408 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2409 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2414 ret = davinci_mcasp_set_ch_constraints(mcasp);
2420 ret = davinci_mcasp_get_dma_type(mcasp);
2426 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
2447 &davinci_mcasp_dai[mcasp->op_mode], 1);
2453 ret = davinci_mcasp_init_gpiochip(mcasp);
2473 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2474 struct davinci_mcasp_context *context = &mcasp->context;
2479 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2481 if (mcasp->txnumevt) {
2482 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2483 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2485 if (mcasp->rxnumevt) {
2486 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2487 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2490 for (i = 0; i < mcasp->num_serializer; i++)
2491 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2499 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2500 struct davinci_mcasp_context *context = &mcasp->context;
2505 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2507 if (mcasp->txnumevt) {
2508 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2509 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2511 if (mcasp->rxnumevt) {
2512 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2513 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2516 for (i = 0; i < mcasp->num_serializer; i++)
2517 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2535 .name = "davinci-mcasp",