Lines Matching defs:mvc

52 	struct tegra210_mvc *mvc = dev_get_drvdata(dev);
54 regmap_read(mvc->regmap, TEGRA210_MVC_CTRL, &(mvc->ctrl_value));
56 regcache_cache_only(mvc->regmap, true);
57 regcache_mark_dirty(mvc->regmap);
64 struct tegra210_mvc *mvc = dev_get_drvdata(dev);
66 regcache_cache_only(mvc->regmap, false);
67 regcache_sync(mvc->regmap);
69 regmap_write(mvc->regmap, TEGRA210_MVC_CTRL, mvc->ctrl_value);
70 regmap_update_bits(mvc->regmap,
92 static void tegra210_mvc_conv_vol(struct tegra210_mvc *mvc, u8 chan, s32 val)
100 if (mvc->curve_type == CURVE_POLY) {
103 mvc->volume[chan] = ((val * (1<<8)) / 100) << 16;
106 mvc->volume[chan] = (val * (1<<8)) / 100;
113 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
117 regmap_read(mvc->regmap, TEGRA210_MVC_CTRL, &val);
178 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
182 err = regmap_read_poll_timeout(mvc->regmap, TEGRA210_MVC_SWITCH,
198 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
219 regmap_update_bits_check(mvc->regmap, TEGRA210_MVC_CTRL,
225 regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
229 regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
264 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
266 s32 val = mvc->volume[chan];
268 if (mvc->curve_type == CURVE_POLY) {
293 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
295 int old_volume = mvc->volume[chan];
304 tegra210_mvc_conv_vol(mvc, chan, ucontrol->value.integer.value[0]);
306 if (mvc->volume[chan] == old_volume) {
312 regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
316 regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
320 mvc->volume[i] = mvc->volume[chan];
324 regmap_write(mvc->regmap,
326 mvc->volume[chan]);
328 regmap_write(mvc->regmap, mc->reg, mvc->volume[chan]);
330 regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
354 static void tegra210_mvc_reset_vol_settings(struct tegra210_mvc *mvc,
360 if (mvc->curve_type == CURVE_POLY) {
362 mvc->volume[i] = TEGRA210_MVC_INIT_VOL_DEFAULT_POLY;
365 mvc->volume[i] = TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR;
371 regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
373 mvc->curve_type <<
378 regmap_write(mvc->regmap,
380 mvc->volume[i]);
381 regmap_write(mvc->regmap,
383 mvc->volume[i]);
387 regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
398 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
400 ucontrol->value.enumerated.item[0] = mvc->curve_type;
409 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
412 regmap_read(mvc->regmap, TEGRA210_MVC_ENABLE, &value);
419 if (mvc->curve_type == ucontrol->value.enumerated.item[0])
422 mvc->curve_type = ucontrol->value.enumerated.item[0];
424 tegra210_mvc_reset_vol_settings(mvc, cmpnt->dev);
429 static int tegra210_mvc_set_audio_cif(struct tegra210_mvc *mvc,
456 tegra_set_cif(mvc->regmap, reg, &cif_conf);
466 struct tegra210_mvc *mvc = snd_soc_dai_get_drvdata(dai);
475 regmap_write(mvc->regmap, TEGRA210_MVC_SOFT_RESET, 1);
477 err = regmap_read_poll_timeout(mvc->regmap, TEGRA210_MVC_SOFT_RESET,
485 err = tegra210_mvc_set_audio_cif(mvc, params, TEGRA210_MVC_RX_CIF_CTRL);
492 err = tegra210_mvc_set_audio_cif(mvc, params, TEGRA210_MVC_TX_CIF_CTRL);
498 tegra210_mvc_write_ram(mvc->regmap);
501 regmap_write(mvc->regmap, TEGRA210_MVC_POLY_N1, gain_params.poly_n1);
502 regmap_write(mvc->regmap, TEGRA210_MVC_POLY_N2, gain_params.poly_n2);
503 regmap_write(mvc->regmap, TEGRA210_MVC_DURATION, gain_params.duration);
506 regmap_write(mvc->regmap, TEGRA210_MVC_DURATION_INV,
701 { .compatible = "nvidia,tegra210-mvc" },
709 struct tegra210_mvc *mvc;
713 mvc = devm_kzalloc(dev, sizeof(*mvc), GFP_KERNEL);
714 if (!mvc)
717 dev_set_drvdata(dev, mvc);
719 mvc->curve_type = CURVE_LINEAR;
720 mvc->ctrl_value = TEGRA210_MVC_CTRL_DEFAULT;
726 mvc->regmap = devm_regmap_init_mmio(dev, regs,
728 if (IS_ERR(mvc->regmap)) {
730 return PTR_ERR(mvc->regmap);
733 regcache_cache_only(mvc->regmap, true);
745 tegra210_mvc_reset_vol_settings(mvc, &pdev->dev);
764 .name = "tegra210-mvc",