Lines Matching refs:sdev
64 static int hda_setup_bdle(struct snd_sof_dev *sdev,
70 struct hdac_bus *bus = sof_to_bus(sdev);
78 dev_err(sdev->dev, "error: stream frags exceeded\n");
112 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
116 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
122 dev_dbg(sdev->dev, "period_bytes:0x%x\n", period_bytes);
128 dev_dbg(sdev->dev, "periods:%d\n", periods);
149 offset = hda_setup_bdle(sdev, dmab,
153 offset = hda_setup_bdle(sdev, dmab,
161 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
168 if (!sdev->bar[HDA_DSP_SPIB_BAR]) {
169 dev_err(sdev->dev, "error: address of spib capability is NULL\n");
176 snd_sof_dsp_update_bits(sdev, HDA_DSP_SPIB_BAR,
181 sof_io_write(sdev, hstream->spib_addr, size);
188 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags)
190 const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata);
191 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
192 struct hdac_bus *bus = sof_to_bus(sdev);
219 dev_err(sdev->dev, "error: no free %s streams\n",
234 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
244 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag)
246 const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata);
247 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
248 struct hdac_bus *bus = sof_to_bus(sdev);
280 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
286 dev_err(sdev->dev, "%s: stream_tag %d not opened!\n",
294 static int hda_dsp_stream_reset(struct snd_sof_dev *sdev, struct hdac_stream *hstream)
301 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST,
304 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset);
309 dev_err(sdev->dev, "timeout waiting for stream reset\n");
316 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST, 0x0);
321 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset);
326 dev_err(sdev->dev, "timeout waiting for stream to exit reset\n");
333 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
345 if (!sdev->dspless_mode_selected)
352 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
356 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
363 ret = snd_sof_dsp_read_poll_timeout(sdev,
375 if (!sdev->dspless_mode_selected)
380 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
385 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
392 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
397 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
403 dev_err(sdev->dev, "error: unknown command: %d\n", cmd);
410 dev_err(sdev->dev,
420 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream,
430 dev_err(sdev->dev, "error: no stream available\n");
435 dev_err(sdev->dev, "error: no dma buffer allocated!\n");
443 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
446 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
452 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
454 dev_err(sdev->dev, "error: set up of BDL failed\n");
459 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
462 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
467 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
472 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
477 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
481 snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_LTRP,
485 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
495 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
500 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
501 struct hdac_bus *bus = sof_to_bus(sdev);
509 dev_err(sdev->dev, "error: no stream available\n");
514 dev_err(sdev->dev, "error: no dma buffer allocated!\n");
523 if (!sdev->dspless_mode_selected)
524 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
528 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
532 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
541 dev_err(sdev->dev,
548 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
554 ret = hda_dsp_stream_reset(sdev, hstream);
562 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
565 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
570 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
574 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
583 dev_err(sdev->dev,
590 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
597 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
599 dev_err(sdev->dev, "error: set up of BDL failed\n");
604 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
610 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
626 if (!sdev->dspless_mode_selected && (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK))
628 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
632 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
637 if (!sdev->dspless_mode_selected && (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK))
639 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
643 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
648 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
651 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
657 !(snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE)
659 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
661 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
667 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
674 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
686 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
695 ret = hda_dsp_stream_reset(sdev, hstream);
699 if (!sdev->dspless_mode_selected) {
700 struct hdac_bus *bus = sof_to_bus(sdev);
706 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
711 hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0);
719 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev)
721 struct hdac_bus *bus = sof_to_bus(sdev);
728 status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
730 trace_sof_intel_hda_dsp_check_stream_irq(sdev, status);
810 struct snd_sof_dev *sdev = context;
811 struct hdac_bus *bus = sof_to_bus(sdev);
823 status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
830 active |= hda_codec_check_rirb_status(sdev);
839 int hda_dsp_stream_init(struct snd_sof_dev *sdev)
841 struct hdac_bus *bus = sof_to_bus(sdev);
844 struct pci_dev *pci = to_pci_dev(sdev->dev);
850 gcap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCAP);
851 dev_dbg(sdev->dev, "hda global caps = 0x%x\n", gcap);
858 dev_dbg(sdev->dev, "detected %d playback and %d capture streams\n",
862 dev_err(sdev->dev, "error: too many playback streams %d\n",
868 dev_err(sdev->dev, "error: too many capture streams %d\n",
881 dev_err(sdev->dev, "error: posbuffer dma alloc failed\n");
892 dev_err(sdev->dev, "error: RB alloc failed\n");
900 hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream),
905 hda_stream->sdev = sdev;
910 if (sdev->bar[HDA_DSP_PP_BAR]) {
911 hext_stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
914 hext_stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
922 if (sdev->bar[HDA_DSP_SPIB_BAR]) {
923 hstream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
927 hstream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
936 hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
952 dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
966 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) {
967 struct sof_ipc4_fw_data *ipc4_data = sdev->private;
977 void hda_dsp_stream_free(struct snd_sof_dev *sdev)
979 struct hdac_bus *bus = sof_to_bus(sdev);
1002 devm_kfree(sdev->dev, hda_stream);
1012 struct snd_sof_dev *sdev = hda_stream->sdev;
1036 pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
1056 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
1067 pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
1081 dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n",
1098 * @sdev: SOF device
1104 u64 hda_dsp_get_stream_llp(struct snd_sof_dev *sdev,
1115 * pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
1136 * @sdev: SOF device
1142 u64 hda_dsp_get_stream_ldp(struct snd_sof_dev *sdev,
1153 * pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +