soc/qcom/lpass-hdmi.c

26 	unsigned int ret;
77 	ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_RESET);
78 	if (ret)
79 		return ret;
81 	ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_CLEAR);
82 	if (ret)
83 		return ret;
85 	ret = regmap_field_write(drvdata->hdmitx_legacy_en, LPASS_HDMITX_LEGACY_DISABLE);
86 	if (ret)
87 		return ret;
89 	ret = regmap_field_write(drvdata->hdmitx_parity_calc_en, HDMITX_PARITY_CALC_EN);
90 	if (ret)
91 		return ret;
93 	ret = regmap_field_write(drvdata->vbit_ctl->replace_vbit, REPLACE_VBIT);
94 	if (ret)
95 		return ret;
97 	ret = regmap_field_write(drvdata->vbit_ctl->vbit_stream, LINEAR_PCM_DATA);
98 	if (ret)
99 		return ret;
101 	ret = regmap_field_write(drvdata->hdmitx_ch_msb[0], ch_sts_buf1);
102 	if (ret)
103 		return ret;
105 	ret = regmap_field_write(drvdata->hdmitx_ch_lsb[0], ch_sts_buf0);
106 	if (ret)
107 		return ret;
109 	ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_chs, HW_MODE);
110 	if (ret)
111 		return ret;
113 	ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_chs_sel, SW_MODE);
114 	if (ret)
115 		return ret;
117 	ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_usr, HW_MODE);
118 	if (ret)
119 		return ret;
121 	ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_usr_sel, SW_MODE);
122 	if (ret)
123 		return ret;
125 	ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
126 	if (ret)
127 		return ret;
129 	ret = regmap_field_write(meta_ctl->as_sdp_cc, channels - 1);
130 	if (ret)
131 		return ret;
133 	ret = regmap_field_write(meta_ctl->as_sdp_ct, LPASS_META_DEFAULT_VAL);
134 	if (ret)
135 		return ret;
137 	ret = regmap_field_write(meta_ctl->aif_db4, LPASS_META_DEFAULT_VAL);
138 	if (ret)
139 		return ret;
141 	ret = regmap_field_write(meta_ctl->frequency, sampling_freq);
142 	if (ret)
143 		return ret;
145 	ret = regmap_field_write(meta_ctl->mst_index, LPASS_META_DEFAULT_VAL);
146 	if (ret)
147 		return ret;
149 	ret = regmap_field_write(meta_ctl->dptx_index, LPASS_META_DEFAULT_VAL);
150 	if (ret)
151 		return ret;
153 	ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
154 	if (ret)
155 		return ret;
157 	ret = regmap_field_write(sstream_ctl->dma_sel, ch);
158 	if (ret)
159 		return ret;
161 	ret = regmap_field_write(sstream_ctl->auto_bbit_en, LPASS_SSTREAM_DEFAULT_ENABLE);
162 	if (ret)
163 		return ret;
165 	ret = regmap_field_write(sstream_ctl->layout, LPASS_SSTREAM_DEFAULT_DISABLE);
166 	if (ret)
167 		return ret;
169 	ret = regmap_field_write(sstream_ctl->layout_sp, LPASS_LAYOUT_SP_DEFAULT);
170 	if (ret)
171 		return ret;
173 	ret = regmap_field_write(sstream_ctl->dp_audio, LPASS_SSTREAM_DEFAULT_ENABLE);
174 	if (ret)
175 		return ret;
177 	ret = regmap_field_write(sstream_ctl->set_sp_on_en, LPASS_SSTREAM_DEFAULT_ENABLE);
178 	if (ret)
179 		return ret;
181 	ret = regmap_field_write(sstream_ctl->dp_sp_b_hw_en, LPASS_SSTREAM_DEFAULT_ENABLE);
182 	if (ret)
183 		return ret;
185 	ret = regmap_field_write(sstream_ctl->dp_staffing_en, LPASS_SSTREAM_DEFAULT_ENABLE);
187 	return ret;
193 	int ret;
196 	ret = regmap_field_write(drvdata->sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
197 	if (ret)
198 		return ret;
200 	ret = regmap_field_write(drvdata->meta_ctl->mute, LPASS_MUTE_DISABLE);
202 	return ret;
211 	int ret = -EINVAL;
217 		ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
218 		if (ret)
219 			return ret;
221 		ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_DISABLE);
222 		if (ret)
223 			return ret;
229 		ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
230 		if (ret)
231 			return ret;
233 		ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
234 		if (ret)
235 			return ret;
237 		ret = regmap_field_write(sstream_ctl->dp_audio, 0);
238 		if (ret)
239 			return ret;
243 	return ret;