soc/qcom/lpass-cdc-dma.c

65 	int ret;
71 		ret = LPASS_CDC_DMA_INTERFACE1;
76 		ret = LPASS_CDC_DMA_INTERFACE2;
81 		ret = LPASS_CDC_DMA_INTERFACE3;
86 		ret = LPASS_CDC_DMA_INTERFACE4;
91 		ret = LPASS_CDC_DMA_INTERFACE5;
96 		ret = LPASS_CDC_DMA_INTERFACE6;
101 		ret = LPASS_CDC_DMA_INTERFACE7;
106 		ret = LPASS_CDC_DMA_INTERFACE8;
111 		ret = LPASS_CDC_DMA_INTERFACE9;
114 		ret  = LPASS_CDC_DMA_INTERFACE10;
117 		ret = -EINVAL;
120 	return ret;
130 	int ret, id, codec_intf;
143 	ret = regmap_fields_write(dmactl->codec_intf, id, codec_intf);
144 	if (ret) {
145 		dev_err(dev, "error writing to dmactl codec_intf reg field: %d\n", ret);
146 		return ret;
148 	ret = regmap_fields_write(dmactl->codec_fs_sel, id, 0x0);
149 	if (ret) {
150 		dev_err(dev, "error writing to dmactl codec_fs_sel reg field: %d\n", ret);
151 		return ret;
153 	ret = regmap_fields_write(dmactl->codec_fs_delay, id, 0x0);
154 	if (ret) {
155 		dev_err(dev, "error writing to dmactl codec_fs_delay reg field: %d\n", ret);
156 		return ret;
158 	ret = regmap_fields_write(dmactl->codec_pack, id, 0x1);
159 	if (ret) {
160 		dev_err(dev, "error writing to dmactl codec_pack reg field: %d\n", ret);
161 		return ret;
163 	ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_ON);
164 	if (ret) {
165 		dev_err(dev, "error writing to dmactl codec_enable reg field: %d\n", ret);
166 		return ret;
220 	unsigned int ret, regval;
249 	ret = regmap_fields_write(dmactl->codec_channel, id, regval);
250 	if (ret) {
252 			"error writing to dmactl codec_channel reg field: %d\n", ret);
253 		return ret;
263 	int ret = 0, id;
278 		ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_OFF);
279 		if (ret) {
281 				"error writing to dmactl codec_enable reg: %d\n", ret);
282 			return ret;
286 		ret = -EINVAL;
290 	return ret;