mediatek/mt8186/mt8186-afe-clk.c

77 	int ret;
79 	ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
81 	if (ret) {
84 			aud_clks[clk_id], ret);
85 		return ret;
94 	int ret;
97 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
98 		if (ret) {
100 				__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
101 			return ret;
103 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
105 		if (ret) {
108 				aud_clks[CLK_TOP_APLL1_CK], ret);
109 			return ret;
113 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
114 		if (ret) {
116 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
117 			return ret;
119 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
121 		if (ret) {
124 				aud_clks[CLK_TOP_APLL1_D8], ret);
125 			return ret;
128 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
130 		if (ret) {
133 				aud_clks[CLK_CLK26M], ret);
134 			return ret;
138 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
140 		if (ret) {
143 				aud_clks[CLK_CLK26M], ret);
144 			return ret;
155 	int ret;
158 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
159 		if (ret) {
161 				__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
162 			return ret;
164 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
166 		if (ret) {
169 				aud_clks[CLK_TOP_APLL2_CK], ret);
170 			return ret;
174 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
175 		if (ret) {
177 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
178 			return ret;
180 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
182 		if (ret) {
185 				aud_clks[CLK_TOP_APLL2_D8], ret);
186 			return ret;
189 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
191 		if (ret) {
194 				aud_clks[CLK_CLK26M], ret);
195 			return ret;
199 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
201 		if (ret) {
204 				aud_clks[CLK_CLK26M], ret);
205 			return ret;
216 	int ret = 0;
220 		ret = clk_prepare_enable(afe_priv->clk[i]);
221 		if (ret) {
223 				__func__, aud_clks[i], ret);
224 			return ret;
243 	int ret = 0;
245 	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
246 	if (ret) {
248 			__func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
252 	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
253 	if (ret) {
255 			__func__, aud_clks[CLK_INFRA_AUDIO_26M], ret);
259 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
260 	if (ret) {
262 			__func__, aud_clks[CLK_MUX_AUDIO], ret);
265 	ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
267 	if (ret) {
270 			aud_clks[CLK_CLK26M], ret);
274 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
275 	if (ret) {
277 			__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
280 	ret = mt8186_set_audio_int_bus_parent(afe,
282 	if (ret)
285 	ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],
287 	if (ret) {
290 			aud_clks[CLK_TOP_APLL2_CK], ret);
294 	ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
295 	if (ret) {
297 			__func__, aud_clks[CLK_AFE], ret);
317 	return ret;
335 	int ret;
338 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
339 	if (ret) {
341 			 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
344 	ret = mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
345 	if (ret)
356 	return ret;
362 	int ret;
365 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
366 	if (ret) {
368 			 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
371 	ret = mt8186_set_audio_int_bus_parent(afe,
373 	if (ret)
384 	return ret;
390 	int ret;
395 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
396 	if (ret) {
398 			__func__, aud_clks[CLK_APLL22M], ret);
402 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
403 	if (ret) {
405 			__func__, aud_clks[CLK_APLL1_TUNER], ret);
422 	return ret;
443 	int ret;
448 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
449 	if (ret) {
451 			__func__, aud_clks[CLK_APLL24M], ret);
455 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
456 	if (ret) {
458 			__func__, aud_clks[CLK_APLL2_TUNER], ret);
475 	return ret;
548 	int ret;
552 		ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
553 		if (ret) {
555 				__func__, aud_clks[m_sel_id], ret);
556 			return ret;
558 		ret = clk_set_parent(afe_priv->clk[m_sel_id],
560 		if (ret) {
563 				aud_clks[apll_clk_id], ret);
564 			return ret;
569 	ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
570 	if (ret) {
572 			__func__, aud_clks[div_clk_id], ret);
573 		return ret;
575 	ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
576 	if (ret) {
578 			__func__, aud_clks[div_clk_id], rate, ret);
579 		return ret;
612 			dev_err(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",