mediatek/mt8183/mt8183-afe-clk.c

105 			dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
118 	int ret;
120 	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
121 	if (ret) {
123 			__func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
127 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
128 	if (ret) {
130 			__func__, aud_clks[CLK_MUX_AUDIO], ret);
134 	ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
136 	if (ret) {
139 			aud_clks[CLK_CLK26M], ret);
143 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
144 	if (ret) {
146 			__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
150 	ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
152 	if (ret) {
155 			aud_clks[CLK_TOP_SYSPLL_D2_D4], ret);
159 	ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
160 	if (ret) {
162 			__func__, aud_clks[CLK_AFE], ret);
166 	ret = clk_prepare_enable(afe_priv->clk[CLK_I2S1_BCLK_SW]);
167 	if (ret) {
169 			__func__, aud_clks[CLK_I2S1_BCLK_SW], ret);
173 	ret = clk_prepare_enable(afe_priv->clk[CLK_I2S2_BCLK_SW]);
174 	if (ret) {
176 			__func__, aud_clks[CLK_I2S2_BCLK_SW], ret);
180 	ret = clk_prepare_enable(afe_priv->clk[CLK_I2S3_BCLK_SW]);
181 	if (ret) {
183 			__func__, aud_clks[CLK_I2S3_BCLK_SW], ret);
187 	ret = clk_prepare_enable(afe_priv->clk[CLK_I2S4_BCLK_SW]);
188 	if (ret) {
190 			__func__, aud_clks[CLK_I2S4_BCLK_SW], ret);
211 	return ret;
234 	int ret;
237 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
238 		if (ret) {
240 				__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
243 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
245 		if (ret) {
248 				aud_clks[CLK_TOP_APLL1_CK], ret);
253 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
254 		if (ret) {
256 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
259 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
261 		if (ret) {
264 				aud_clks[CLK_TOP_APLL1_D8], ret);
268 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
270 		if (ret) {
273 				aud_clks[CLK_CLK26M], ret);
278 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
280 		if (ret) {
283 				aud_clks[CLK_CLK26M], ret);
302 	return ret;
308 	int ret;
311 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
312 		if (ret) {
314 				__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
317 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
319 		if (ret) {
322 				aud_clks[CLK_TOP_APLL2_CK], ret);
327 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
328 		if (ret) {
330 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
333 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
335 		if (ret) {
338 				aud_clks[CLK_TOP_APLL2_D8], ret);
342 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
344 		if (ret) {
347 				aud_clks[CLK_CLK26M], ret);
352 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
354 		if (ret) {
357 				aud_clks[CLK_CLK26M], ret);
376 	return ret;
382 	int ret;
387 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
388 	if (ret) {
390 			__func__, aud_clks[CLK_APLL22M], ret);
394 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
395 	if (ret) {
397 			__func__, aud_clks[CLK_APLL1_TUNER], ret);
414 	return ret;
436 	int ret;
441 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
442 	if (ret) {
444 			__func__, aud_clks[CLK_APLL24M], ret);
448 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
449 	if (ret) {
451 			__func__, aud_clks[CLK_APLL2_TUNER], ret);
468 	return ret;
550 	int ret;
558 		ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
559 		if (ret) {
561 				__func__, aud_clks[m_sel_id], ret);
564 		ret = clk_set_parent(afe_priv->clk[m_sel_id],
566 		if (ret) {
569 				aud_clks[apll_clk_id], ret);
575 	ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
576 	if (ret) {
578 			__func__, aud_clks[div_clk_id], ret);
581 	ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
582 	if (ret) {
585 			rate, ret);
598 	return ret;