Lines Matching refs:afe_priv
36 struct mt6797_afe_private *afe_priv = afe->platform_priv;
39 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
41 if (!afe_priv->clk)
45 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
46 if (IS_ERR(afe_priv->clk[i])) {
49 PTR_ERR(afe_priv->clk[i]));
50 return PTR_ERR(afe_priv->clk[i]);
59 struct mt6797_afe_private *afe_priv = afe->platform_priv;
62 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD]);
69 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
76 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD]);
83 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD],
84 afe_priv->clk[CLK_CLK26M]);
92 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
102 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
104 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);
106 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
108 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);
115 struct mt6797_afe_private *afe_priv = afe->platform_priv;
117 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
118 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);
119 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
120 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);