intel/skylake/skl-sst-cldma.c

18 static void skl_cldma_int_enable(struct sst_dsp *ctx)
20 	sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
24 void skl_cldma_int_disable(struct sst_dsp *ctx)
26 	sst_dsp_shim_update_bits_unlocked(ctx,
30 static void skl_cldma_stream_run(struct sst_dsp  *ctx, bool enable)
35 	sst_dsp_shim_update_bits_unlocked(ctx,
43 		val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) &
53 		dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
56 static void skl_cldma_stream_clear(struct sst_dsp  *ctx)
59 	skl_cldma_stream_run(ctx, 0);
61 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
63 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
65 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
67 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
70 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
71 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
73 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
74 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
78 static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
83 	int remaining = ctx->cl_dev.bufsize;
86 	ctx->cl_dev.frags = 0;
102 		ctx->cl_dev.frags++;
112 static void skl_cldma_setup_controller(struct sst_dsp  *ctx,
116 	skl_cldma_stream_clear(ctx);
117 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
119 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
122 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
123 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
124 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
126 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
128 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
130 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
134 static void skl_cldma_setup_spb(struct sst_dsp  *ctx,
138 		sst_dsp_shim_update_bits_unlocked(ctx,
143 	sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
146 static void skl_cldma_cleanup_spb(struct sst_dsp  *ctx)
148 	sst_dsp_shim_update_bits_unlocked(ctx,
153 	sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
156 static void skl_cldma_cleanup(struct sst_dsp  *ctx)
158 	skl_cldma_cleanup_spb(ctx);
159 	skl_cldma_stream_clear(ctx);
161 	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
162 	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
165 int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
169 	if (!wait_event_timeout(ctx->cl_dev.wait_queue,
170 				ctx->cl_dev.wait_condition,
172 		dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
177 	dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
178 	if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
179 		dev_err(ctx->dev, "%s: DMA Error\n", __func__);
184 	ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
188 static void skl_cldma_stop(struct sst_dsp *ctx)
190 	skl_cldma_stream_run(ctx, false);
193 static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
196 	dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
197 	dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
198 			ctx->cl_dev.dma_buffer_offset, trigger);
199 	dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
206 	if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
207 		unsigned int size_b = ctx->cl_dev.bufsize -
208 					ctx->cl_dev.dma_buffer_offset;
209 		memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
213 		ctx->cl_dev.dma_buffer_offset = 0;
216 	memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
219 	if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
220 		ctx->cl_dev.dma_buffer_offset = 0;
222 		ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
224 	ctx->cl_dev.wait_condition = false;
227 		skl_cldma_int_enable(ctx);
229 	ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
231 		ctx->cl_dev.ops.cl_trigger(ctx, true);
250 skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin,
263 	dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);
266 		if (bytes_left > ctx->cl_dev.bufsize) {
272 			if (ctx->cl_dev.curr_spib_pos == 0)
273 				ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;
275 			size = ctx->cl_dev.bufsize;
276 			skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);
280 				ret = skl_cldma_wait_interruptible(ctx);
282 					skl_cldma_stop(ctx);
287 			skl_cldma_int_disable(ctx);
289 			if ((ctx->cl_dev.curr_spib_pos + bytes_left)
290 							<= ctx->cl_dev.bufsize) {
291 				ctx->cl_dev.curr_spib_pos += bytes_left;
294 					(ctx->cl_dev.bufsize -
295 					ctx->cl_dev.curr_spib_pos);
296 				ctx->cl_dev.curr_spib_pos = excess_bytes;
300 			skl_cldma_fill_buffer(ctx, size,
312 void skl_cldma_process_intr(struct sst_dsp *ctx)
317 		sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);
320 		ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
322 		ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;
324 	ctx->cl_dev.wait_condition = true;
325 	wake_up(&ctx->cl_dev.wait_queue);
328 int skl_cldma_prepare(struct sst_dsp *ctx)
333 	ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;
336 	ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
337 	ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
338 	ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
339 	ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
340 	ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
341 	ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
342 	ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
343 	ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
346 	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, ctx->dev, ctx->cl_dev.bufsize,
347 				  &ctx->cl_dev.dmab_data);
349 		dev_err(ctx->dev, "Alloc buffer for base fw failed: %x\n", ret);
354 	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, ctx->dev, BDL_SIZE, &ctx->cl_dev.dmab_bdl);
356 		dev_err(ctx->dev, "Alloc buffer for blde failed: %x\n", ret);
357 		ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
360 	bdl = (__le32 *)ctx->cl_dev.dmab_bdl.area;
363 	ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
364 			&bdl, ctx->cl_dev.bufsize, 1);
365 	ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
366 			ctx->cl_dev.bufsize, ctx->cl_dev.frags);
368 	ctx->cl_dev.curr_spib_pos = 0;
369 	ctx->cl_dev.dma_buffer_offset = 0;
370 	init_waitqueue_head(&ctx->cl_dev.wait_queue);