intel/skylake/cnl-sst-dsp.c

27 cnl_dsp_core_set_reset_state(struct sst_dsp *ctx, unsigned int core_mask)
30 	sst_dsp_shim_update_bits_unlocked(ctx,
35 	return sst_dsp_register_poll(ctx,
44 cnl_dsp_core_unset_reset_state(struct sst_dsp *ctx, unsigned int core_mask)
47 	sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
51 	return sst_dsp_register_poll(ctx,
59 static bool is_cnl_dsp_core_enable(struct sst_dsp *ctx, unsigned int core_mask)
64 	val = sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPCS);
71 	dev_dbg(ctx->dev, "DSP core(s) enabled? %d: core_mask %#x\n",
77 static int cnl_dsp_reset_core(struct sst_dsp *ctx, unsigned int core_mask)
80 	sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
85 	return cnl_dsp_core_set_reset_state(ctx, core_mask);
88 static int cnl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask)
93 	ret = cnl_dsp_core_unset_reset_state(ctx, core_mask);
98 	sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
101 	if (!is_cnl_dsp_core_enable(ctx, core_mask)) {
102 		cnl_dsp_reset_core(ctx, core_mask);
103 		dev_err(ctx->dev, "DSP core mask %#x enable failed\n",
111 static int cnl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask)
114 	sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
119 	return sst_dsp_register_poll(ctx, CNL_ADSP_REG_ADSPCS,
126 static int cnl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask)
129 	sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
133 	return sst_dsp_register_poll(ctx,
141 int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask)
146 	ret = cnl_dsp_core_power_up(ctx, core_mask);
148 		dev_dbg(ctx->dev, "DSP core mask %#x power up failed",
153 	return cnl_dsp_start_core(ctx, core_mask);
156 int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask)
160 	ret = cnl_dsp_reset_core(ctx, core_mask);
162 		dev_err(ctx->dev, "DSP core mask %#x reset failed\n",
168 	ret = cnl_dsp_core_power_down(ctx, core_mask);
170 		dev_err(ctx->dev, "DSP core mask %#x power down failed\n",
175 	if (is_cnl_dsp_core_enable(ctx, core_mask)) {
176 		dev_err(ctx->dev, "DSP core mask %#x disable failed\n",
186 	struct sst_dsp *ctx = dev_id;
190 	spin_lock(&ctx->spinlock);
192 	val = sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPIS);
193 	ctx->intr_status = val;
196 		spin_unlock(&ctx->spinlock);
201 		cnl_ipc_int_disable(ctx);
205 	spin_unlock(&ctx->spinlock);
220 void cnl_ipc_int_enable(struct sst_dsp *ctx)
222 	sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_ADSPIC,
226 void cnl_ipc_int_disable(struct sst_dsp *ctx)
228 	sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPIC,
232 void cnl_ipc_op_int_enable(struct sst_dsp *ctx)
235 	sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
240 	sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
245 void cnl_ipc_op_int_disable(struct sst_dsp *ctx)
248 	sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
252 	sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
256 bool cnl_ipc_int_status(struct sst_dsp *ctx)
258 	return sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPIS) &