atom/sst/sst_acpi.c

148 static int sst_platform_get_resources(struct intel_sst_drv *ctx)
151 	struct platform_device *pdev = to_platform_device(ctx->dev);
156 					ctx->pdata->res_info->acpi_lpe_res_index);
158 		dev_err(ctx->dev, "Invalid SHIM base from IFWI\n");
161 	dev_info(ctx->dev, "LPE base: %#x size:%#x", (unsigned int) rsrc->start,
164 	ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset;
165 	ctx->iram_end =  ctx->iram_base + ctx->pdata->res_info->iram_size - 1;
166 	dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base);
167 	ctx->iram = devm_ioremap(ctx->dev, ctx->iram_base,
168 					 ctx->pdata->res_info->iram_size);
169 	if (!ctx->iram) {
170 		dev_err(ctx->dev, "unable to map IRAM\n");
174 	ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset;
175 	ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1;
176 	dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base);
177 	ctx->dram = devm_ioremap(ctx->dev, ctx->dram_base,
178 					 ctx->pdata->res_info->dram_size);
179 	if (!ctx->dram) {
180 		dev_err(ctx->dev, "unable to map DRAM\n");
184 	ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset;
185 	dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add);
186 	ctx->shim = devm_ioremap(ctx->dev, ctx->shim_phy_add,
187 					ctx->pdata->res_info->shim_size);
188 	if (!ctx->shim) {
189 		dev_err(ctx->dev, "unable to map SHIM\n");
194 	ctx->shim_phy_add = ctx->pdata->res_info->shim_phy_addr;
197 	ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset;
198 	dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add);
199 	ctx->mailbox = devm_ioremap(ctx->dev, ctx->mailbox_add,
200 					    ctx->pdata->res_info->mbox_size);
201 	if (!ctx->mailbox) {
202 		dev_err(ctx->dev, "unable to map mailbox\n");
207 	ctx->mailbox_add = ctx->info.mailbox_start;
210 					ctx->pdata->res_info->acpi_ddr_index);
212 		dev_err(ctx->dev, "Invalid DDR base from IFWI\n");
215 	ctx->ddr_base = rsrc->start;
216 	ctx->ddr_end = rsrc->end;
217 	dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base);
218 	ctx->ddr = devm_ioremap(ctx->dev, ctx->ddr_base,
220 	if (!ctx->ddr) {
221 		dev_err(ctx->dev, "unable to map DDR\n");
226 	ctx->irq_num = platform_get_irq(pdev,
227 				ctx->pdata->res_info->acpi_ipc_irq_index);
228 	if (ctx->irq_num <= 0)
229 		return ctx->irq_num < 0 ? ctx->irq_num : -EIO;
238 	struct intel_sst_drv *ctx;
279 	ret = sst_alloc_drv_context(&ctx, dev, dev_id);
313 	ctx->pdata = pdata;
314 	strcpy(ctx->firmware_name, mach->fw_filename);
316 	ret = sst_platform_get_resources(ctx);
320 	ret = sst_context_init(ctx);
324 	sst_configure_runtime_pm(ctx);
325 	platform_set_drvdata(pdev, ctx);
339 	struct intel_sst_drv *ctx;
341 	ctx = platform_get_drvdata(pdev);
342 	sst_context_cleanup(ctx);