Lines Matching refs:chv3_i2s_wr
101 static inline void chv3_i2s_wr(struct chv3_i2s_dev *i2s, int offset, u32 val)
159 chv3_i2s_wr(i2s, I2S_RX_ENABLE, 0);
161 chv3_i2s_wr(i2s, I2S_TX_ENABLE, 0);
212 chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_RX_BIT);
213 chv3_i2s_wr(i2s, I2S_RX_BASE_ADDR, substream->dma_buffer.addr);
214 chv3_i2s_wr(i2s, I2S_RX_BUFFER_SIZE, buffer_bytes);
215 chv3_i2s_wr(i2s, I2S_RX_IRQ, (period_size << 8) | 1);
216 chv3_i2s_wr(i2s, I2S_RX_ENABLE, 1);
218 chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_TX_BIT);
219 chv3_i2s_wr(i2s, I2S_TX_BASE_ADDR, substream->dma_buffer.addr);
220 chv3_i2s_wr(i2s, I2S_TX_BUFFER_SIZE, buffer_bytes);
221 chv3_i2s_wr(i2s, I2S_TX_IRQ, ((period_bytes / i2s->tx_bytes_to_fetch) << 8) | 1);
222 chv3_i2s_wr(i2s, I2S_TX_ENABLE, 1);
263 chv3_i2s_wr(i2s, I2S_RX_CONSUMER_IDX, idx);
265 chv3_i2s_wr(i2s, I2S_TX_PRODUCER_IDX, idx);