soc/codecs/wm8978.c

408 static void pll_factors(struct snd_soc_component *component,
424 		dev_warn(component->dev,
471 static int wm8978_configure_pll(struct snd_soc_component *component)
473 	struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
505 		dev_dbg(component->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div);
507 		snd_soc_component_update_bits(component, WM8978_GPIO_CONTROL, 0x30,
533 	dev_dbg(component->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
536 	pll_factors(component, &pll_div, f2, wm8978->f_mclk);
538 	dev_dbg(component->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
542 	snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
544 	snd_soc_component_write(component, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n);
545 	snd_soc_component_write(component, WM8978_PLL_K1, pll_div.k >> 18);
546 	snd_soc_component_write(component, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
547 	snd_soc_component_write(component, WM8978_PLL_K3, pll_div.k & 0x1ff);
550 	snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
554 		snd_soc_component_update_bits(component, WM8978_GPIO_CONTROL, 7, 4);
565 	struct snd_soc_component *component = codec_dai->component;
566 	struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
588 			ret = wm8978_configure_pll(component);
593 		snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x1c, div);
599 	dev_dbg(component->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
610 	struct snd_soc_component *component = codec_dai->component;
611 	struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
614 	dev_dbg(component->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq);
621 			ret = wm8978_configure_pll(component);
631 		snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x100, 0);
634 		snd_soc_component_update_bits(component, WM8978_GPIO_CONTROL, 7, 0);
637 		snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
651 	struct snd_soc_component *component = codec_dai->component;
656 	u16 iface = snd_soc_component_read(component, WM8978_AUDIO_INTERFACE) & ~0x198;
657 	u16 clk = snd_soc_component_read(component, WM8978_CLOCKING);
659 	dev_dbg(component->dev, "%s\n", __func__);
707 	snd_soc_component_write(component, WM8978_AUDIO_INTERFACE, iface);
708 	snd_soc_component_write(component, WM8978_CLOCKING, clk);
720 	struct snd_soc_component *component = dai->component;
721 	struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
723 	u16 iface_ctl = snd_soc_component_read(component, WM8978_AUDIO_INTERFACE) & ~0x60;
725 	u16 add_ctl = snd_soc_component_read(component, WM8978_ADDITIONAL_CONTROL) & ~0xe;
726 	u16 clking = snd_soc_component_read(component, WM8978_CLOCKING);
781 			int ret = wm8978_configure_pll(component);
812 		dev_warn(component->dev, "Imprecise sampling rate: %uHz%s\n",
817 	dev_dbg(component->dev, "%s: width %d, rate %u, MCLK divisor #%d\n", __func__,
821 	snd_soc_component_update_bits(component, WM8978_CLOCKING, 0xe0, best << 5);
823 	snd_soc_component_write(component, WM8978_AUDIO_INTERFACE, iface_ctl);
824 	snd_soc_component_write(component, WM8978_ADDITIONAL_CONTROL, add_ctl);
829 			snd_soc_component_update_bits(component, WM8978_CLOCKING,
833 			snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x100, 0);
841 	struct snd_soc_component *component = dai->component;
843 	dev_dbg(component->dev, "%s: %d\n", __func__, mute);
846 		snd_soc_component_update_bits(component, WM8978_DAC_CONTROL, 0x40, 0x40);
848 		snd_soc_component_update_bits(component, WM8978_DAC_CONTROL, 0x40, 0);
853 static int wm8978_set_bias_level(struct snd_soc_component *component,
856 	u16 power1 = snd_soc_component_read(component, WM8978_POWER_MANAGEMENT_1) & ~3;
862 		snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1, power1);
868 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
870 			snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1,
876 		snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1, power1);
880 		snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, ~0x20, 0);
881 		snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_2, 0);
882 		snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_3, 0);
886 	dev_dbg(component->dev, "%s: %d, %x\n", __func__, level, power1);
924 static int wm8978_suspend(struct snd_soc_component *component)
926 	struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
928 	snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
930 	snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1, 0);
937 static int wm8978_resume(struct snd_soc_component *component)
939 	struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
944 	snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
948 		snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
972 static int wm8978_probe(struct snd_soc_component *component)
974 	struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
989 		snd_soc_component_update_bits(component, update_reg[i], 0x100, 0x100);