soc/codecs/lpass-rx-macro.c

533 	IIR0 = 0,
635 	"ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
2652 		if (strnstr(w->name, "IIR0", sizeof("IIR0"))) {
2839 	SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
2842 	SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
2845 	SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
2848 	SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
2885 	RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
2886 	RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
2887 	RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
2888 	RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
2889 	RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
2971 	SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
2972 	SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
2973 	SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
2974 	SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
2993 	SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL,
3133 	{"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
3143 	{"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
3153 	{"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
3164 	{"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
3174 	{"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
3184 	{"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
3195 	{"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
3205 	{"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
3215 	{"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
3298 	{"IIR0", NULL, "RX_MCLK"},
3299 	{"IIR0", NULL, "IIR0 INP0 MUX"},
3300 	{"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3301 	{"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3302 	{"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3303 	{"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3304 	{"IIR0 INP0 MUX", "RX0", "RX_RX0"},
3305 	{"IIR0 INP0 MUX", "RX1", "RX_RX1"},
3306 	{"IIR0 INP0 MUX", "RX2", "RX_RX2"},
3307 	{"IIR0 INP0 MUX", "RX3", "RX_RX3"},
3308 	{"IIR0 INP0 MUX", "RX4", "RX_RX4"},
3309 	{"IIR0 INP0 MUX", "RX5", "RX_RX5"},
3310 	{"IIR0", NULL, "IIR0 INP1 MUX"},
3311 	{"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3312 	{"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3313 	{"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3314 	{"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3315 	{"IIR0 INP1 MUX", "RX0", "RX_RX0"},
3316 	{"IIR0 INP1 MUX", "RX1", "RX_RX1"},
3317 	{"IIR0 INP1 MUX", "RX2", "RX_RX2"},
3318 	{"IIR0 INP1 MUX", "RX3", "RX_RX3"},
3319 	{"IIR0 INP1 MUX", "RX4", "RX_RX4"},
3320 	{"IIR0 INP1 MUX", "RX5", "RX_RX5"},
3321 	{"IIR0", NULL, "IIR0 INP2 MUX"},
3322 	{"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3323 	{"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3324 	{"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3325 	{"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3326 	{"IIR0 INP2 MUX", "RX0", "RX_RX0"},
3327 	{"IIR0 INP2 MUX", "RX1", "RX_RX1"},
3328 	{"IIR0 INP2 MUX", "RX2", "RX_RX2"},
3329 	{"IIR0 INP2 MUX", "RX3", "RX_RX3"},
3330 	{"IIR0 INP2 MUX", "RX4", "RX_RX4"},
3331 	{"IIR0 INP2 MUX", "RX5", "RX_RX5"},
3332 	{"IIR0", NULL, "IIR0 INP3 MUX"},
3333 	{"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3334 	{"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3335 	{"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3336 	{"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3337 	{"IIR0 INP3 MUX", "RX0", "RX_RX0"},
3338 	{"IIR0 INP3 MUX", "RX1", "RX_RX1"},
3339 	{"IIR0 INP3 MUX", "RX2", "RX_RX2"},
3340 	{"IIR0 INP3 MUX", "RX3", "RX_RX3"},
3341 	{"IIR0 INP3 MUX", "RX4", "RX_RX4"},
3342 	{"IIR0 INP3 MUX", "RX5", "RX_RX5"},
3390 	{"SRC0", NULL, "IIR0"},