Lines Matching refs:u32
194 u32 rx_data_one_line:1;
195 u32 rx_ws_pol:1;
196 u32 rx_ws_wid:7;
197 u32 rx_frm_len:5;
198 u32 rx_sa_size:2;
199 u32 tx_data_one_line:1;
200 u32 tx_ws_pol:1;
201 u32 tx_ws_wid:7;
202 u32 tx_frm_len:5;
203 u32 tx_sa_size:2;
205 u32 ulval;
210 u32 tx_en_ch1:1;
211 u32 tx_en_ch2:1;
212 u32 tx_en_ch3:1;
213 u32 tx_en_ch4:1;
214 u32 tx_en_ch5:1;
215 u32 tx_en_ch6:1;
216 u32 tx_slot_1:5;
217 u32 tx_slot_2:5;
218 u32 tx_slot_3:5;
219 u32 tx_slot_4:5;
220 u32 res:1;
221 u32 tx_data_neg_bclk:1;
222 u32 tx_master:1;
223 u32 tx_tri_n:1;
224 u32 tx_endian_sel:1;
225 u32 tx_dstart_dly:1;
227 u32 ulval;
232 u32 rx_en_ch1:1;
233 u32 rx_en_ch2:1;
234 u32 rx_en_ch3:1;
235 u32 rx_en_ch4:1;
236 u32 rx_en_ch5:1;
237 u32 rx_en_ch6:1;
238 u32 rx_slot_1:5;
239 u32 rx_slot_2:5;
240 u32 rx_slot_3:5;
241 u32 rx_slot_4:5;
242 u32 res:1;
243 u32 rx_data_neg_bclk:1;
244 u32 rx_master:1;
245 u32 rx_tri_n:1;
246 u32 rx_endian_sel:1;
247 u32 rx_dstart_dly:1;
249 u32 ulval;
254 u32 rx_mute:1;
255 u32 tx_mute:1;
256 u32 reserved:1;
257 u32 dac_34_independent:1;
258 u32 dac_bclk_lrck_share:1;
259 u32 bclk_lrck_share_en:1;
260 u32 reserved2:2;
261 u32 rx_last_dac_ch_en:1;
262 u32 rx_last_dac_ch:3;
263 u32 tx_last_adc_ch_en:1;
264 u32 tx_last_adc_ch:3;
265 u32 rx_slot_5:5;
266 u32 rx_slot_6:5;
267 u32 reserved3:6;
269 u32 ulval;
274 u32 tx_slot_5:5;
275 u32 reserved:3;
276 u32 tx_slot_6:5;
277 u32 reserved2:3;
278 u32 reserved3:8;
279 u32 i2s_pcm_clk_div:7;
280 u32 i2s_pcm_clk_div_chan_en:1;
282 u32 ulval;
287 u32 reserved:5;
288 u32 rx_pause_cycles:3;
289 u32 rx_pause_start_pos:8;
290 u32 reserved2:5;
291 u32 tx_pause_cycles:3;
292 u32 tx_pause_start_pos:8;
294 u32 ulval;
299 u32 pull_down_eapd:2;
300 u32 input_en_eapd_pad:1;
301 u32 push_pull_mode:1;
302 u32 eapd_pad_output_driver:2;
303 u32 pll_source:1;
304 u32 i2s_bclk_en:1;
305 u32 i2s_bclk_invert:1;
306 u32 pll_ref_clock:1;
307 u32 class_d_shield_clk:1;
308 u32 audio_pll_bypass_mode:1;
309 u32 reserved:4;
311 u32 ulval;