Lines Matching defs:gclk
296 * @gclk: generic clock
306 struct clk *gclk;
477 clk_disable_unprepare(dev->gclk);
479 ret = clk_set_min_rate(dev->gclk, params_rate(params) *
483 "unable to set gclk min rate: rate %u * ratio %u + 1\n",
486 clk_prepare_enable(dev->gclk);
489 ret = clk_prepare_enable(dev->gclk);
491 dev_err(dev->dev, "unable to enable gclk: %d\n", ret);
716 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled
754 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled
856 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled
873 rate = clk_get_rate(dev->gclk);
1044 clk_disable_unprepare(spdifrx->gclk);
1059 ret = clk_prepare_enable(spdifrx->gclk);
1068 clk_disable_unprepare(spdifrx->gclk);
1126 dev->gclk = devm_clk_get(&pdev->dev, "gclk");
1127 if (IS_ERR(dev->gclk)) {
1128 err = PTR_ERR(dev->gclk);
1135 * Signal control need a valid rate on gclk. hw_params() configures
1138 * gclk at a valid rate, here, in initialization, to simplify the
1141 clk_set_min_rate(dev->gclk, 48000 * SPDIFRX_GCLK_RATIO_MIN + 1);