pci/rme9652/hdsp.c

1722 	ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1737 	val = ucontrol->value.integer.value[0] & 1;
2063 	ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2072 	change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2074 		hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2521 	ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2534 	val = ucontrol->value.integer.value[0] & 1;
2567 	ucontrol->value.integer.value[0] = hdsp->use_midi_work;
2580 	val = ucontrol->value.integer.value[0] & 1;
2604 	uinfo->value.integer.min = 0;
2605 	uinfo->value.integer.max = 65536;
2606 	uinfo->value.integer.step = 1;
2617 	source = ucontrol->value.integer.value[0];
2618 	destination = ucontrol->value.integer.value[1];
2626 	ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2643 	source = ucontrol->value.integer.value[0];
2644 	destination = ucontrol->value.integer.value[1];
2651 	gain = ucontrol->value.integer.value[2];
2848 	uinfo->value.integer.min = -5000;
2849 	uinfo->value.integer.max = 5000;
2857 	ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2869 	val = ucontrol->value.integer.value[0];
3125 	ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3149 	val = ucontrol->value.integer.value[0] & 1;
3177 	ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3201 	val = ucontrol->value.integer.value[0] & 1;
3281 	ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel);
3291 	const bool enable = ucontrol->value.integer.value[0] & 1;
4357 			.integer = 1,
4364 			.integer = 1,
4371 			.integer = 1,
4388 			.integer = 1,
4395 			.integer = 1,
4402 			.integer = 1,
4419 			.integer = 1,
4426 			.integer = 1,
4433 			.integer = 1,
4450 			.integer = 1,
4457 			.integer = 1,
4464 			.integer = 1,