pci/rme9652/hdsp.c

450 	u32                   control_register;	     /* cached value */
1017 	hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1047 	s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1048 	hdsp_write(s, HDSP_controlRegister, s->control_register);
1053 	s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1054 	hdsp_write(s, HDSP_controlRegister, s->control_register);
1075 	s->control_register &= ~HDSP_LatencyMask;
1076 	s->control_register |= hdsp_encode_latency(n);
1078 	hdsp_write(s, HDSP_controlRegister, s->control_register);
1117 	if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1215 	hdsp->control_register &= ~HDSP_FrequencyMask;
1216 	hdsp->control_register |= rate_bits;
1217 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1360 		hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1362 		hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1363 	hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1380 		if (!(hdsp->control_register & ie)) {
1382 			hdsp->control_register |= ie;
1385 		hdsp->control_register &= ~ie;
1388 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1612 	hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1613 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1641 	return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1646 	hdsp->control_register &= ~HDSP_SPDIFInputMask;
1647 	hdsp->control_register |= hdsp_encode_spdif_in(in);
1648 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1699 	return (hdsp->control_register & regmask) ? 1 : 0;
1705 		hdsp->control_register |= regmask;
1707 		hdsp->control_register &= ~regmask;
1708 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1899 	if (hdsp->control_register & HDSP_ClockModeMaster)
1932 	if (hdsp->control_register & HDSP_ClockModeMaster) {
1967 			hdsp->control_register &= ~HDSP_ClockModeMaster;
1968 			hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2003 	hdsp->control_register |= HDSP_ClockModeMaster;
2004 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2089 	switch (hdsp->control_register & HDSP_DAGainMask) {
2103 	hdsp->control_register &= ~HDSP_DAGainMask;
2106 		hdsp->control_register |= HDSP_DAGainHighGain;
2109 		hdsp->control_register |= HDSP_DAGainPlus4dBu;
2112 		hdsp->control_register |= HDSP_DAGainMinus10dBV;
2118 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2168 	switch (hdsp->control_register & HDSP_ADGainMask) {
2182 	hdsp->control_register &= ~HDSP_ADGainMask;
2185 		hdsp->control_register |= HDSP_ADGainMinus10dBV;
2188 		hdsp->control_register |= HDSP_ADGainPlus4dBu;
2191 		hdsp->control_register |= HDSP_ADGainLowGain;
2197 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2247 	switch (hdsp->control_register & HDSP_PhoneGainMask) {
2261 	hdsp->control_register &= ~HDSP_PhoneGainMask;
2264 		hdsp->control_register |= HDSP_PhoneGain0dB;
2267 		hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2270 		hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2276 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2330 	switch (hdsp->control_register & HDSP_SyncRefMask) {
2351 	hdsp->control_register &= ~HDSP_SyncRefMask;
2354 		hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2357 		hdsp->control_register |= HDSP_SyncRef_ADAT2;
2360 		hdsp->control_register |= HDSP_SyncRef_ADAT3;
2363 		hdsp->control_register |= HDSP_SyncRef_SPDIF;
2366 		hdsp->control_register |= HDSP_SyncRef_WORD;
2369 		hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2374 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2956 	switch (hdsp->control_register & HDSP_RPM_Inp12) {
2981 	hdsp->control_register &= ~HDSP_RPM_Inp12;
2984 		hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2989 		hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2992 		hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2995 		hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3001 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3041 	switch (hdsp->control_register & HDSP_RPM_Inp34) {
3066 	hdsp->control_register &= ~HDSP_RPM_Inp34;
3069 		hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3074 		hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3077 		hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3080 		hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3086 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3117 	return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3133 		hdsp->control_register |= HDSP_RPM_Bypass;
3135 		hdsp->control_register &= ~HDSP_RPM_Bypass;
3136 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3169 	return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3185 		hdsp->control_register |= HDSP_RPM_Disconnect;
3187 		hdsp->control_register &= ~HDSP_RPM_Disconnect;
3188 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3407 	snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3449 	x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3454 	snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3584 		if (hdsp->control_register & HDSP_RPM_Bypass)
3588 		if (hdsp->control_register & HDSP_RPM_Disconnect)
3593 		switch (hdsp->control_register & HDSP_RPM_Inp12) {
3613 		switch (hdsp->control_register & HDSP_RPM_Inp34) {
3634 		if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3639 		if (hdsp->control_register & HDSP_SPDIFProfessional)
3644 		if (hdsp->control_register & HDSP_SPDIFEmphasis)
3649 		if (hdsp->control_register & HDSP_SPDIFNonAudio)
3754 		if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3818 	hdsp->control_register = HDSP_ClockModeMaster |
3824 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3851 		hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3852 		hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3912 			hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3913 			hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3923 			hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3924 			hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
4055 		hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4056 		hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
5239 	hdsp->control_register = 0;
5383 		hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5384 		hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);