pci/pcxhr/pcxhr_hwdep.c

32 	struct pcxhr_rmh rmh;
45 	pcxhr_init_rmh(&rmh, CMD_SUPPORTED);
46 	err = pcxhr_send_msg(mgr, &rmh);
50 	if ((rmh.stat[0] & MASK_FIRST_FIELD) < mgr->playback_chips * 2)
53 	if (((rmh.stat[0] >> (2 * FIELD_SIZE)) & MASK_FIRST_FIELD) <
57 	if ((rmh.stat[1] & 0x5F) < card_streams)
60 	if (((rmh.stat[1] >> 7) & 0x5F) < PCXHR_PLAYBACK_STREAMS)
64 		    rmh.stat[2], rmh.stat[3]);
66 	pcxhr_init_rmh(&rmh, CMD_VERSION);
68 	rmh.cmd[0] |= mgr->firmware_num;
70 	rmh.cmd[1] = (1<<23) + mgr->granularity;
71 	rmh.cmd_len = 2;
72 	err = pcxhr_send_msg(mgr, &rmh);
76 		"PCXHR DSP version is %d.%d.%d\n", (rmh.stat[0]>>16)&0xff,
77 		    (rmh.stat[0]>>8)&0xff, rmh.stat[0]&0xff);
78 	mgr->dsp_version = rmh.stat[0];
90 	struct pcxhr_rmh rmh;
93 	pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
94 	rmh.cmd[0] |= IO_NUM_REG_STATUS;
95 	rmh.cmd[1]  = REG_STATUS_OPTIONS;
96 	rmh.cmd_len = 2;
97 	err = pcxhr_send_msg(mgr, &rmh);
101 	if ((rmh.stat[1] & REG_STATUS_OPT_DAUGHTER_MASK) ==
111 	pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
112 	rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
114 		rmh.cmd[1]  = 1;	/* unmute digital plugs */
115 		rmh.cmd_len = 2;
117 	err = pcxhr_send_msg(mgr, &rmh);
123 	struct pcxhr_rmh rmh;
129 		pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
130 		rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
131 		pcxhr_send_msg(mgr, &rmh);
159 	struct pcxhr_rmh rmh;
176 	pcxhr_init_rmh(&rmh, CMD_RES_PIPE);
177 	pcxhr_set_pipe_cmd_params(&rmh, is_capture, pin,
179 	rmh.cmd[1] |= 0x020000; /* add P_PCM_ONLY_MASK */
182 	  rmh.cmd[rmh.cmd_len++] = (audio_count == 1) ? 0x01 : 0x03;
184 	err = pcxhr_send_msg(mgr, &rmh);
201 	struct pcxhr_rmh rmh;
216 	pcxhr_init_rmh(&rmh, CMD_FREE_PIPE);
217 	pcxhr_set_pipe_cmd_params(&rmh, pipe->is_capture, pipe->first_audio,
219 	err = pcxhr_send_msg(mgr, &rmh);