pci/hda/patch_hdmi.c

424 	/* no pin nid is associated with the kctl now
425 	 * tbd: associate pin nid to eld ctl later
673 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
676 	snd_hda_set_dev_select(codec, nid, dev_id);
678 	return snd_hdmi_get_eld(codec, nid, buf, eld_size);
793 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
797 	int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
813 	check_presence_and_report(codec, jack->nid, jack->dev_id);
823 		codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
826 	check_presence_and_report(codec, jack->nid, jack->dev_id);
884 		hda_nid_t cvt_nid, hda_nid_t nid)
894 	if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
895 		snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
898 		pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
900 		codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
1093 	hda_nid_t nid;
1126 		nid = per_pin->pin_nid;
1134 		dev_id_saved = snd_hda_get_dev_select(codec, nid);
1135 		snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1136 		curr = snd_hda_codec_read(codec, nid, 0,
1139 			snd_hda_set_dev_select(codec, nid, dev_id_saved);
1152 					  cvt_idx, nid);
1153 				snd_hda_codec_write_cache(codec, nid, 0,
1159 		snd_hda_set_dev_select(codec, nid, dev_id_saved);
1170 	/* On Intel platform, the mapping of converter nid to
1172 	 * The pin nid may be 0, this means all pins will not
1212 	hinfo->nid = per_cvt->cvt_nid;
1278 	hinfo->nid = per_cvt->cvt_nid;
1308 			hinfo->nid = 0;
1451 	per_pin->cvt_nid = hinfo->nid;
1453 	mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1461 	snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1463 	non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
2031 		hda_nid_t nid = start_nid + i;
2033 		caps = get_wcaps(codec, nid);
2039 			hdmi_add_cvt(codec, nid);
2044 		hda_nid_t nid = start_nid + i;
2046 		caps = get_wcaps(codec, nid);
2052 			hdmi_add_pin(codec, nid);
2089 	hda_nid_t cvt_nid = hinfo->nid;
2165 	snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2181 	if (hinfo->nid) {
2187 		cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2194 		hinfo->nid = 0;
2613 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2618 	tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2624 		snd_hda_codec_write_cache(codec, nid, 0,
3230 	pstr->nid = per_cvt->cvt_nid;
3643 	.nid = nvhdmi_master_con_nid_7x,
3888 	unsigned int nid = NVIDIA_AFG_NID;
3898 		nid = cvt_nid;
3901 	value = snd_hda_codec_read(codec, nid, 0,
3906 	snd_hda_codec_write(codec, nid, 0,
3909 	snd_hda_codec_write(codec, nid, 0,
3914 	snd_hda_codec_write(codec, nid, 0,
3933 		snd_hda_codec_write(codec, nid, 0,
3935 		snd_hda_codec_write(codec, nid, 0,
3945 		snd_hda_codec_write(codec, nid, 0,
3964 	tegra_hdmi_set_format(codec, hinfo->nid, format);
3974 	tegra_hdmi_set_format(codec, hinfo->nid, 0);
4126 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
4131 	return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,