Lines Matching refs:clock
86 /* Map the DSP clock detect bits to the generic driver clock detect bits */
166 /* Only set the clock for internal mode. Do not return failure,
170 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
190 u16 clock;
197 clock = LAYLA20_CLOCK_INTERNAL;
200 clock = LAYLA20_CLOCK_SPDIF;
203 clock = LAYLA20_CLOCK_WORD;
206 clock = LAYLA20_CLOCK_SUPER;
210 "Input clock 0x%x not supported for Layla24\n",
216 chip->comm_page->input_clock = cpu_to_le16(clock);
228 static int set_output_clock(struct echoaudio *chip, u16 clock)
230 switch (clock) {
232 clock = LAYLA20_OUTPUT_CLOCK_SUPER;
235 clock = LAYLA20_OUTPUT_CLOCK_WORD;
238 dev_err(chip->card->dev, "set_output_clock wrong clock\n");
245 chip->comm_page->output_clock = cpu_to_le16(clock);
246 chip->output_clock = clock;