Lines Matching refs:clock
191 disconnects clock inputs. You should use this information to determine which
197 /* Map the DSP clock detect bits to the generic driver clock
245 * 48 kHz, internal clock, S/PDIF RCA mode */
260 u32 control_reg, clock, base_rate, frq_reg;
262 /* Only set the clock for internal mode. */
265 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
282 clock = E3G_96KHZ;
285 clock = E3G_88KHZ;
288 clock = E3G_48KHZ;
291 clock = E3G_44KHZ;
294 clock = E3G_32KHZ;
297 clock = E3G_CONTINUOUS_CLOCK;
299 clock |= E3G_DOUBLE_SPEED_MODE;
303 control_reg |= clock;
319 "SetSampleRate: %d clock %x\n", rate, control_reg);
327 /* Set the sample clock source to internal, S/PDIF, ADAT */
328 static int set_input_clock(struct echoaudio *chip, u16 clock)
333 /* Mask off the clock select bits */
338 switch (clock) {
366 "Input clock 0x%x not supported for Echo3G\n", clock);
370 chip->input_clock = clock;
381 /* Set clock to "internal" if it's not compatible with the new mode */