Lines Matching refs:bus
15 static void azx_clear_corbrp(struct hdac_bus *bus)
20 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
25 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
26 snd_hdac_chip_readw(bus, CORBRP));
28 snd_hdac_chip_writew(bus, CORBRP, 0);
30 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
35 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
36 snd_hdac_chip_readw(bus, CORBRP));
41 * @bus: HD-audio core bus
43 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
45 WARN_ON_ONCE(!bus->rb.area);
47 spin_lock_irq(&bus->reg_lock);
49 bus->corb.addr = bus->rb.addr;
50 bus->corb.buf = (__le32 *)bus->rb.area;
51 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
52 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
55 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
57 snd_hdac_chip_writew(bus, CORBWP, 0);
60 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
61 if (!bus->corbrp_self_clear)
62 azx_clear_corbrp(bus);
65 if (!bus->use_pio_for_commands)
66 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
69 bus->rirb.addr = bus->rb.addr + 2048;
70 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
71 bus->rirb.wp = bus->rirb.rp = 0;
72 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
73 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
74 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
77 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
79 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
81 snd_hdac_chip_writew(bus, RINTCNT, 1);
83 if (bus->not_use_interrupts)
84 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN);
86 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
88 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
89 spin_unlock_irq(&bus->reg_lock);
94 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
99 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
104 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
111 * @bus: HD-audio core bus
113 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
115 spin_lock_irq(&bus->reg_lock);
117 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
118 snd_hdac_chip_writeb(bus, CORBCTL, 0);
119 spin_unlock_irq(&bus->reg_lock);
121 hdac_wait_for_cmd_dmas(bus);
123 spin_lock_irq(&bus->reg_lock);
125 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
126 spin_unlock_irq(&bus->reg_lock);
140 static int snd_hdac_bus_wait_for_pio_response(struct hdac_bus *bus,
147 if (snd_hdac_chip_readw(bus, IRS) & AZX_IRS_VALID) {
149 bus->rirb.res[addr] = snd_hdac_chip_readl(bus, IR);
155 dev_dbg_ratelimited(bus->dev, "get_response_pio timeout: IRS=%#x\n",
156 snd_hdac_chip_readw(bus, IRS));
158 bus->rirb.res[addr] = -1;
165 * @bus: HD-audio core bus
170 static int snd_hdac_bus_send_cmd_pio(struct hdac_bus *bus, unsigned int val)
176 spin_lock_irq(&bus->reg_lock);
180 if (!((snd_hdac_chip_readw(bus, IRS) & AZX_IRS_BUSY))) {
182 snd_hdac_chip_updatew(bus, IRS, AZX_IRS_VALID, AZX_IRS_VALID);
183 snd_hdac_chip_writel(bus, IC, val);
185 snd_hdac_chip_updatew(bus, IRS, AZX_IRS_BUSY, AZX_IRS_BUSY);
187 ret = snd_hdac_bus_wait_for_pio_response(bus, addr);
193 dev_dbg_ratelimited(bus->dev, "send_cmd_pio timeout: IRS=%#x, val=%#x\n",
194 snd_hdac_chip_readw(bus, IRS), val);
197 spin_unlock_irq(&bus->reg_lock);
204 * @bus: HD-audio core bus
210 static int snd_hdac_bus_get_response_pio(struct hdac_bus *bus,
214 *res = bus->rirb.res[addr];
221 * @bus: HD-audio core bus
226 static int snd_hdac_bus_send_cmd_corb(struct hdac_bus *bus, unsigned int val)
231 spin_lock_irq(&bus->reg_lock);
233 bus->last_cmd[azx_command_addr(val)] = val;
236 wp = snd_hdac_chip_readw(bus, CORBWP);
239 spin_unlock_irq(&bus->reg_lock);
245 rp = snd_hdac_chip_readw(bus, CORBRP);
248 spin_unlock_irq(&bus->reg_lock);
252 bus->rirb.cmds[addr]++;
253 bus->corb.buf[wp] = cpu_to_le32(val);
254 snd_hdac_chip_writew(bus, CORBWP, wp);
256 spin_unlock_irq(&bus->reg_lock);
265 * @bus: HD-audio core bus
268 * The caller needs bus->reg_lock spinlock before calling this.
270 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
276 wp = snd_hdac_chip_readw(bus, RIRBWP);
282 if (wp == bus->rirb.wp)
284 bus->rirb.wp = wp;
286 while (bus->rirb.rp != wp) {
287 bus->rirb.rp++;
288 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
290 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
291 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
292 res = le32_to_cpu(bus->rirb.buf[rp]);
295 dev_err(bus->dev,
297 res, res_ex, bus->rirb.rp, wp);
300 snd_hdac_bus_queue_event(bus, res, res_ex);
301 else if (bus->rirb.cmds[addr]) {
302 bus->rirb.res[addr] = res;
303 bus->rirb.cmds[addr]--;
304 if (!bus->rirb.cmds[addr] &&
305 waitqueue_active(&bus->rirb_wq))
306 wake_up(&bus->rirb_wq);
308 dev_err_ratelimited(bus->dev,
310 res, res_ex, bus->last_cmd[addr]);
318 * @bus: HD-audio core bus
324 static int snd_hdac_bus_get_response_rirb(struct hdac_bus *bus,
336 spin_lock_irq(&bus->reg_lock);
337 if (!bus->polling_mode)
338 prepare_to_wait(&bus->rirb_wq, &wait,
340 if (bus->polling_mode)
341 snd_hdac_bus_update_rirb(bus);
342 if (!bus->rirb.cmds[addr]) {
344 *res = bus->rirb.res[addr]; /* the last value */
345 if (!bus->polling_mode)
346 finish_wait(&bus->rirb_wq, &wait);
347 spin_unlock_irq(&bus->reg_lock);
350 spin_unlock_irq(&bus->reg_lock);
354 if (!bus->polling_mode) {
356 } else if (bus->needs_damn_long_delay ||
359 dev_dbg_ratelimited(bus->dev,
361 bus->last_cmd[addr]);
371 if (!bus->polling_mode)
372 finish_wait(&bus->rirb_wq, &wait);
379 * @bus: HD-audio core bus
384 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
386 if (bus->use_pio_for_commands)
387 return snd_hdac_bus_send_cmd_pio(bus, val);
389 return snd_hdac_bus_send_cmd_corb(bus, val);
395 * @bus: HD-audio core bus
401 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
404 if (bus->use_pio_for_commands)
405 return snd_hdac_bus_get_response_pio(bus, addr, res);
407 return snd_hdac_bus_get_response_rirb(bus, addr, res);
414 * @bus: the pointer to bus object
418 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
424 offset = snd_hdac_chip_readw(bus, LLCH);
428 cur_cap = _snd_hdac_chip_readl(bus, offset);
430 dev_dbg(bus->dev, "Capability version: 0x%x\n",
433 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
437 dev_dbg(bus->dev, "Invalid capability reg read\n");
443 dev_dbg(bus->dev, "Found ML capability\n");
444 bus->mlcap = bus->remap_addr + offset;
448 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
449 bus->gtscap = bus->remap_addr + offset;
454 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
455 bus->ppcap = bus->remap_addr + offset;
460 dev_dbg(bus->dev, "Found SPB capability\n");
461 bus->spbcap = bus->remap_addr + offset;
466 dev_dbg(bus->dev, "Found DRSM capability\n");
467 bus->drsmcap = bus->remap_addr + offset;
471 dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
479 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
498 * @bus: HD-audio core bus
502 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
507 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
510 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
518 * @bus: HD-audio core bus
522 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
526 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
529 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
535 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
541 if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)
542 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
545 snd_hdac_bus_enter_link_reset(bus);
553 snd_hdac_bus_exit_link_reset(bus);
560 if (!snd_hdac_chip_readb(bus, GCTL)) {
561 dev_dbg(bus->dev, "controller not ready!\n");
566 if (!bus->codec_mask) {
567 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
568 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
576 static void azx_int_enable(struct hdac_bus *bus)
579 snd_hdac_chip_updatel(bus, INTCTL,
585 static void azx_int_disable(struct hdac_bus *bus)
590 list_for_each_entry(azx_dev, &bus->stream_list, list)
594 snd_hdac_chip_writel(bus, INTCTL, 0);
598 static void azx_int_clear(struct hdac_bus *bus)
603 list_for_each_entry(azx_dev, &bus->stream_list, list)
607 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
610 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
613 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
618 * @bus: HD-audio core bus
621 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
623 if (bus->chip_init)
627 snd_hdac_bus_reset_link(bus, full_reset);
630 azx_int_clear(bus);
633 snd_hdac_bus_init_cmd_io(bus);
636 azx_int_enable(bus);
639 if (bus->use_posbuf && bus->posbuf.addr) {
640 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
641 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
644 bus->chip_init = true;
652 * @bus: HD-audio core bus
654 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
656 if (!bus->chip_init)
660 azx_int_disable(bus);
661 azx_int_clear(bus);
664 snd_hdac_bus_stop_cmd_io(bus);
667 if (bus->posbuf.addr) {
668 snd_hdac_chip_writel(bus, DPLBASE, 0);
669 snd_hdac_chip_writel(bus, DPUBASE, 0);
672 bus->chip_init = false;
678 * @bus: HD-audio core bus
684 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
692 list_for_each_entry(azx_dev, &bus->stream_list, list) {
701 ack(bus, azx_dev);
710 * @bus: HD-audio core bus
715 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
719 int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
722 list_for_each_entry(s, &bus->stream_list, list) {
724 err = snd_dma_alloc_pages(dma_type, bus->dev,
734 err = snd_dma_alloc_pages(dma_type, bus->dev,
735 num_streams * 8, &bus->posbuf);
738 list_for_each_entry(s, &bus->stream_list, list)
739 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
742 return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
748 * @bus: HD-audio core bus
750 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
754 list_for_each_entry(s, &bus->stream_list, list) {
759 if (bus->rb.area)
760 snd_dma_free_pages(&bus->rb);
761 if (bus->posbuf.area)
762 snd_dma_free_pages(&bus->posbuf);
774 set_bit(codec->addr, &codec->bus->codec_powered);
776 clear_bit(codec->addr, &codec->bus->codec_powered);