uapi/drm/amdgpu_drm.h

10  * to deal in the Software without restriction, including without limitation
15  * The above copyright notice and this permission notice shall be included in
79  * Memory in this pool could be swapped out to disk if there is pressure.
83  * pages of system memory, allows GPU access system memory in a linearized
122 /* Flag that the memory should be in VRAM and cleared */
126 /* Flag that BO is always valid in this VM */
140  * set in the PTEs when mapping this buffer via GPUVM or
144 /* Flag that BO will be used only in preemptible context, which does
155  * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
156  * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
162  * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
163  * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
170  * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
171  * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
178 	/** physical start_addr alignment in bytes for some HW requirements */
193 	struct drm_amdgpu_gem_create_in		in;
201 /** Opcode to update resource information in the list */
209 	/** Number of BOs in list  */
231 	struct drm_amdgpu_bo_list_in in;
270  * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
316 	struct drm_amdgpu_ctx_in in;
336 	struct drm_amdgpu_vm_in in;
354 	struct drm_amdgpu_sched_in in;
446 	struct drm_amdgpu_gem_mmap_in   in;
467 	struct drm_amdgpu_gem_wait_idle_in  in;
491 	struct drm_amdgpu_wait_cs_in in;
517 	struct drm_amdgpu_wait_fences_in in;
635 	struct drm_amdgpu_cs_in in;
715 	} in;
822 /* Query information about register in MMR address space*/
939 	/* The size of the return value. Just like "size" in "snprintf",
1015 	/** Theoretical max. available memory in the given heap */
1019 	 * Number of bytes allocated in the heap. This includes all processes
1020 	 * and private allocations in the kernel. It changes when new buffers
1028 	 * could be allocated in the given heap
1073 	/** Revision id in PCI Config space */
1078 	/* in KHz */
1192 	/** Handles currently in use for UVD */