fsl/qe/immap_qe.h

24 	__be32	iadd;		/* I-RAM Address Register */
25 	__be32	idata;		/* I-RAM Data Register */
27 	__be32	iready;		/* I-RAM Ready Register */
33 	__be32	qicr;
34 	__be32	qivec;
35 	__be32	qripnr;
36 	__be32	qipnr;
37 	__be32	qipxcc;
38 	__be32	qipycc;
39 	__be32	qipwcc;
40 	__be32	qipzcc;
41 	__be32	qimr;
42 	__be32	qrimr;
43 	__be32	qicnr;
45 	__be32	qiprta;
46 	__be32	qiprtb;
48 	__be32	qricr;
50 	__be32	qhivec;
56 	__be32	cecr;		/* QE command register */
57 	__be32	ceccr;		/* QE controller configuration register */
58 	__be32	cecdr;		/* QE command data register */
63 	__be32	cetscr;		/* QE time-stamp timer control register */
64 	__be32	cetsr1;		/* QE time-stamp register 1 */
65 	__be32	cetsr2;		/* QE time-stamp register 2 */
67 	__be32	cevter;		/* QE virtual tasks event register */
68 	__be32	cevtmr;		/* QE virtual tasks mask register */
88 	__be32	ceurnr;		/* QE microcode revision number register */
94 	__be32	cmxgcr;		/* CMX general clock route register */
95 	__be32	cmxsi1cr_l;	/* CMX SI1 clock route low register */
96 	__be32	cmxsi1cr_h;	/* CMX SI1 clock route high register */
97 	__be32	cmxsi1syr;	/* CMX SI1 SYNC route register */
98 	__be32	cmxucr[4];	/* CMX UCCx clock route registers */
99 	__be32	cmxupcr;	/* CMX UPC clock route register */
135 	__be32	brgc[16];	/* BRG configuration registers */
142 	__be32	spmode;		/* SPI mode register */
152 	__be32	spitd;		/* SPI transmit data register (cpu mode) */
153 	__be32	spird;		/* SPI receive data register (cpu mode) */
196 	__be32	siml1;		/* SI1 multiframe limit register */
229 	__be32	mcce;		/* MCC event register */
230 	__be32	mccm;		/* MCC mask register */
231 	__be32	mccf;		/* MCC configuration register */
232 	__be32	merl;		/* MCC emergency request level register */
238 	__be32	gumr_l;		/* UCCx general mode register (low) */
239 	__be32	gumr_h;		/* UCCx general mode register (high) */
257 	__be32	gumr;		/* UCCx general mode register */
258 	__be32	upsmr;		/* UCCx protocol-specific mode register */
263 	__be32	ucce;		/* UCCx event register */
264 	__be32	uccm;		/* UCCx mask register */
267 	__be32	urfb;		/* UCC receive FIFO base */
273 	__be32	utfb;		/* UCC transmit FIFO base */
282 	__be32	urtry;		/* UCC retry counter register */
297 	__be32	upgcr;		/* UTOPIA/POS general configuration register */
298 	__be32	uplpa;		/* UTOPIA/POS last PHY address */
299 	__be32	uphec;		/* ATM HEC register */
300 	__be32	upuc;		/* UTOPIA/POS UCC configuration */
301 	__be32	updc1;		/* UTOPIA/POS device 1 configuration */
302 	__be32	updc2;		/* UTOPIA/POS device 2 configuration */
303 	__be32	updc3;		/* UTOPIA/POS device 3 configuration */
304 	__be32	updc4;		/* UTOPIA/POS device 4 configuration */
305 	__be32	upstpa;		/* UTOPIA/POS STPA threshold */
307 	__be32	updrs1_h;	/* UTOPIA/POS device 1 rate select */
308 	__be32	updrs1_l;	/* UTOPIA/POS device 1 rate select */
309 	__be32	updrs2_h;	/* UTOPIA/POS device 2 rate select */
310 	__be32	updrs2_l;	/* UTOPIA/POS device 2 rate select */
311 	__be32	updrs3_h;	/* UTOPIA/POS device 3 rate select */
312 	__be32	updrs3_l;	/* UTOPIA/POS device 3 rate select */
313 	__be32	updrs4_h;	/* UTOPIA/POS device 4 rate select */
314 	__be32	updrs4_l;	/* UTOPIA/POS device 4 rate select */
315 	__be32	updrp1;		/* UTOPIA/POS device 1 receive priority low */
316 	__be32	updrp2;		/* UTOPIA/POS device 2 receive priority low */
317 	__be32	updrp3;		/* UTOPIA/POS device 3 receive priority low */
318 	__be32	updrp4;		/* UTOPIA/POS device 4 receive priority low */
319 	__be32	upde1;		/* UTOPIA/POS device 1 event */
320 	__be32	upde2;		/* UTOPIA/POS device 2 event */
321 	__be32	upde3;		/* UTOPIA/POS device 3 event */
322 	__be32	upde4;		/* UTOPIA/POS device 4 event */
344 	__be32	uper1;		/* Device 1 port enable register */
345 	__be32	uper2;		/* Device 2 port enable register */
346 	__be32	uper3;		/* Device 3 port enable register */
347 	__be32	uper4;		/* Device 4 port enable register */
353 	__be32	sdsr;		/* Serial DMA status register */
354 	__be32	sdmr;		/* Serial DMA mode register */
355 	__be32	sdtr1;		/* SDMA system bus threshold register */
356 	__be32	sdtr2;		/* SDMA secondary bus threshold register */
357 	__be32	sdhy1;		/* SDMA system bus hysteresis register */
358 	__be32	sdhy2;		/* SDMA secondary bus hysteresis register */
359 	__be32	sdta1;		/* SDMA system bus address register */
360 	__be32	sdta2;		/* SDMA secondary bus address register */
361 	__be32	sdtm1;		/* SDMA system bus MSNUM register */
362 	__be32	sdtm2;		/* SDMA secondary bus MSNUM register */
364 	__be32	sdaqr;		/* SDMA address bus qualify register */
365 	__be32	sdaqmr;		/* SDMA address bus qualify mask register */
367 	__be32	sdebcr;		/* SDMA CAM entries base register */
373 	__be32	bpdcr;		/* Breakpoint debug command register */
374 	__be32	bpdsr;		/* Breakpoint debug status register */
375 	__be32	bpdmr;		/* Breakpoint debug mask register */
376 	__be32	bprmrr0;	/* Breakpoint request mode risc register 0 */
377 	__be32	bprmrr1;	/* Breakpoint request mode risc register 1 */
379 	__be32	bprmtr0;	/* Breakpoint request mode trb register 0 */
380 	__be32	bprmtr1;	/* Breakpoint request mode trb register 1 */
382 	__be32	bprmir;		/* Breakpoint request mode immediate register */
383 	__be32	bprmsr;		/* Breakpoint request mode serial register */
384 	__be32	bpemr;		/* Breakpoint exit mode register */
393 	__be32 tibcr[16];	/* Trap/instruction breakpoint control regs */
395 	__be32 ibcr0;
396 	__be32 ibs0;
397 	__be32 ibcnr0;
399 	__be32 ibcr1;
400 	__be32 ibs1;
401 	__be32 ibcnr1;
402 	__be32 npcr;
403 	__be32 dbcr;
404 	__be32 dbar;
405 	__be32 dbamr;
406 	__be32 dbsr;
407 	__be32 dbcnr;
409 	__be32 dbdr_h;
410 	__be32 dbdr_l;
411 	__be32 dbdmr_h;
412 	__be32 dbdmr_l;
413 	__be32 bsr;
414 	__be32 bor;
415 	__be32 bior;
417 	__be32 iatr[4];
418 	__be32 eccr;		/* Exception control configuration register */
419 	__be32 eicr;