Lines Matching refs:M4U_LARB5_ID
17 #define M4U_LARB5_ID 5
90 #define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0)
91 #define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1)
92 #define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2)
93 #define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3)
94 #define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4)
95 #define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5)
96 #define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6)
97 #define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7)
98 #define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8)
99 #define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9)
100 #define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10)
101 #define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11)
102 #define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12)
103 #define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13)
104 #define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14)
105 #define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15)
106 #define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16)
107 #define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17)
108 #define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18)
109 #define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19)
110 #define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20)
111 #define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21)
112 #define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22)
113 #define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23)
114 #define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24)
115 #define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25)