drivers/watchdog/stm32_iwdg.c

90 	struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
99 	presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
104 	iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
107 	reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
110 	reg_write(wdt->regs, IWDG_PR, iwdg_pr);
111 	reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
112 	reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
115 	ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
124 	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
131 	struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
136 	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
160 			       struct stm32_iwdg *wdt)
165 	wdt->clk_lsi = devm_clk_get(dev, "lsi");
166 	if (IS_ERR(wdt->clk_lsi))
167 		return dev_err_probe(dev, PTR_ERR(wdt->clk_lsi), "Unable to get lsi clock\n");
170 	if (wdt->data->has_pclk) {
171 		wdt->clk_pclk = devm_clk_get(dev, "pclk");
172 		if (IS_ERR(wdt->clk_pclk))
173 			return dev_err_probe(dev, PTR_ERR(wdt->clk_pclk),
176 		ret = clk_prepare_enable(wdt->clk_pclk);
183 					       wdt->clk_pclk);
188 	ret = clk_prepare_enable(wdt->clk_lsi);
194 				       wdt->clk_lsi);
198 	wdt->rate = clk_get_rate(wdt->clk_lsi);
228 	struct stm32_iwdg *wdt;
231 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
232 	if (!wdt)
235 	wdt->data = of_device_get_match_data(&pdev->dev);
236 	if (!wdt->data)
240 	wdt->regs = devm_platform_ioremap_resource(pdev, 0);
241 	if (IS_ERR(wdt->regs))
242 		return PTR_ERR(wdt->regs);
244 	ret = stm32_iwdg_clk_init(pdev, wdt);
249 	wdd = &wdt->wdd;
254 	wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
255 	wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
256 				    1000) / wdt->rate;
258 	watchdog_set_drvdata(wdd, wdt);
284 	platform_set_drvdata(pdev, wdt);