drivers/watchdog/sp805_wdt.c

3  * drivers/char/watchdog/sp805-wdt.c
37 #define MODULE_NAME		"sp805-wdt"
58  * struct sp805_wdt: sp805 wdt device structure
61  * @base: base address of wdt
62  * @clk: (optional) clock structure of wdt
64  * @adev: amba device structure of wdt
65  * @status: current status of wdt
83 /* returns true if wdt is running; otherwise returns false */
86 	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
87 	u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
95 	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
98 	rate = wdt->rate;
111 	spin_lock(&wdt->lock);
112 	wdt->load_val = load;
115 	spin_unlock(&wdt->lock);
123 	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
126 	spin_lock(&wdt->lock);
127 	load = readl_relaxed(wdt->base + WDTVALUE);
130 	if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
131 		load += wdt->load_val + 1;
132 	spin_unlock(&wdt->lock);
134 	return div_u64(load, wdt->rate);
140 	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
142 	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
143 	writel_relaxed(0, wdt->base + WDTCONTROL);
144 	writel_relaxed(0, wdt->base + WDTLOAD);
145 	writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
148 	readl_relaxed(wdt->base + WDTLOCK);
155 	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
160 		ret = clk_prepare_enable(wdt->clk);
162 			dev_err(&wdt->adev->dev, "clock enable fail");
167 	spin_lock(&wdt->lock);
169 	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
170 	writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
171 	writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
174 		writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
177 	writel_relaxed(LOCK, wdt->base + WDTLOCK);
180 	readl_relaxed(wdt->base + WDTLOCK);
181 	spin_unlock(&wdt->lock);
200 	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
202 	spin_lock(&wdt->lock);
204 	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
205 	writel_relaxed(0, wdt->base + WDTCONTROL);
206 	writel_relaxed(LOCK, wdt->base + WDTLOCK);
209 	readl_relaxed(wdt->base + WDTLOCK);
210 	spin_unlock(&wdt->lock);
212 	clk_disable_unprepare(wdt->clk);
235 	struct sp805_wdt *wdt;
240 	wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
241 	if (!wdt) {
246 	wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
247 	if (IS_ERR(wdt->base))
248 		return PTR_ERR(wdt->base);
257 	wdt->clk = devm_clk_get_optional(&adev->dev, NULL);
258 	if (IS_ERR(wdt->clk))
259 		return dev_err_probe(&adev->dev, PTR_ERR(wdt->clk), "Clock not found\n");
261 	wdt->rate = clk_get_rate(wdt->clk);
262 	if (!wdt->rate)
263 		wdt->rate = rate;
264 	if (!wdt->rate) {
275 	wdt->adev = adev;
276 	wdt->wdd.info = &wdt_info;
277 	wdt->wdd.ops = &wdt_ops;
278 	wdt->wdd.parent = &adev->dev;
280 	spin_lock_init(&wdt->lock);
281 	watchdog_set_nowayout(&wdt->wdd, nowayout);
282 	watchdog_set_drvdata(&wdt->wdd, wdt);
283 	watchdog_set_restart_priority(&wdt->wdd, 128);
284 	watchdog_stop_on_unregister(&wdt->wdd);
290 	wdt->wdd.timeout = DEFAULT_TIMEOUT;
291 	watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
292 	wdt_setload(&wdt->wdd, wdt->wdd.timeout);
295 	 * If HW is already running, enable/reset the wdt and set the running
296 	 * bit to tell the wdt subsystem
298 	if (wdt_is_running(&wdt->wdd)) {
299 		wdt_enable(&wdt->wdd);
300 		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
303 	watchdog_stop_on_reboot(&wdt->wdd);
304 	ret = watchdog_register_device(&wdt->wdd);
307 	amba_set_drvdata(adev, wdt);
319 	struct sp805_wdt *wdt = amba_get_drvdata(adev);
321 	watchdog_unregister_device(&wdt->wdd);
322 	watchdog_set_drvdata(&wdt->wdd, NULL);
327 	struct sp805_wdt *wdt = dev_get_drvdata(dev);
329 	if (watchdog_active(&wdt->wdd))
330 		return wdt_disable(&wdt->wdd);
337 	struct sp805_wdt *wdt = dev_get_drvdata(dev);
339 	if (watchdog_active(&wdt->wdd))
340 		return wdt_enable(&wdt->wdd);