drivers/watchdog/sama5d4_wdt.c

51 #define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS))
53 #define wdt_read(wdt, field) \
54 	readl_relaxed((wdt)->reg_base + (field))
59 static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val)
66 	while (time_before(jiffies, wdt->last_ping + WDT_DELAY))
68 	writel_relaxed(val, wdt->reg_base + field);
69 	wdt->last_ping = jiffies;
72 static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val)
74 	if (time_before(jiffies, wdt->last_ping + WDT_DELAY))
76 	writel_relaxed(val, wdt->reg_base + field);
77 	wdt->last_ping = jiffies;
82 	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
84 	if (wdt->sam9x60_support) {
85 		writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IER);
86 		wdt->mr &= ~AT91_SAM9X60_WDDIS;
88 		wdt->mr &= ~AT91_WDT_WDDIS;
90 	wdt_write(wdt, AT91_WDT_MR, wdt->mr);
97 	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
99 	if (wdt->sam9x60_support) {
100 		writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IDR);
101 		wdt->mr |= AT91_SAM9X60_WDDIS;
103 		wdt->mr |= AT91_WDT_WDDIS;
105 	wdt_write(wdt, AT91_WDT_MR, wdt->mr);
112 	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
114 	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
122 	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
125 	if (wdt->sam9x60_support) {
126 		wdt_write(wdt, AT91_SAM9X60_WLR,
133 	wdt->mr &= ~AT91_WDT_WDV;
134 	wdt->mr |= AT91_WDT_SET_WDV(value);
144 		wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS);
166 	struct sama5d4_wdt *wdt = platform_get_drvdata(dev_id);
169 	if (wdt->sam9x60_support)
170 		reg = wdt_read(wdt, AT91_SAM9X60_ISR);
172 		reg = wdt_read(wdt, AT91_WDT_SR);
183 static int of_sama5d4_wdt_init(struct device_node *np, struct sama5d4_wdt *wdt)
187 	if (wdt->sam9x60_support)
188 		wdt->mr = AT91_SAM9X60_WDDIS;
190 		wdt->mr = AT91_WDT_WDDIS;
194 		wdt->need_irq = true;
197 		wdt->mr |= AT91_WDT_WDIDLEHLT;
200 		wdt->mr |= AT91_WDT_WDDBGHLT;
205 static int sama5d4_wdt_init(struct sama5d4_wdt *wdt)
217 		reg = wdt_read(wdt, AT91_WDT_MR);
218 		if (wdt->sam9x60_support && (!(reg & AT91_SAM9X60_WDDIS)))
219 			wdt_write_nosleep(wdt, AT91_WDT_MR,
221 		else if (!wdt->sam9x60_support &&
223 			wdt_write_nosleep(wdt, AT91_WDT_MR,
227 	if (wdt->sam9x60_support) {
228 		if (wdt->need_irq)
229 			wdt->ir = AT91_SAM9X60_PERINT;
231 			wdt->mr |= AT91_SAM9X60_PERIODRST;
233 		wdt_write(wdt, AT91_SAM9X60_IER, wdt->ir);
234 		wdt_write(wdt, AT91_SAM9X60_WLR, AT91_SAM9X60_SET_COUNTER(val));
236 		wdt->mr |= AT91_WDT_SET_WDD(WDT_SEC2TICKS(MAX_WDT_TIMEOUT));
237 		wdt->mr |= AT91_WDT_SET_WDV(val);
239 		if (wdt->need_irq)
240 			wdt->mr |= AT91_WDT_WDFIEN;
242 			wdt->mr |= AT91_WDT_WDRSTEN;
245 	wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr);
254 	struct sama5d4_wdt *wdt;
260 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
261 	if (!wdt)
264 	wdd = &wdt->wdd;
270 	wdt->last_ping = jiffies;
272 	if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") ||
273 	    of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt"))
274 		wdt->sam9x60_support = true;
276 	watchdog_set_drvdata(wdd, wdt);
282 	wdt->reg_base = regs;
284 	ret = of_sama5d4_wdt_init(dev->of_node, wdt);
288 	if (wdt->need_irq) {
292 			wdt->need_irq = false;
296 	if (wdt->need_irq) {
308 	reg = wdt_read(wdt, AT91_WDT_MR);
310 		wdt->mr &= ~AT91_WDT_WDDIS;
314 	ret = sama5d4_wdt_init(wdt);
325 	platform_set_drvdata(pdev, wdt);
335 		.compatible = "atmel,sama5d4-wdt",
338 		.compatible = "microchip,sam9x60-wdt",
341 		.compatible = "microchip,sama7g5-wdt",
350 	struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
352 	if (watchdog_active(&wdt->wdd))
353 		sama5d4_wdt_stop(&wdt->wdd);
360 	struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
367 	sama5d4_wdt_init(wdt);
369 	if (watchdog_active(&wdt->wdd))
370 		sama5d4_wdt_start(&wdt->wdd);