drivers/watchdog/s3c2410_wdt.c

307 	{ .compatible = "google,gs101-wdt",
309 	{ .compatible = "samsung,s3c2410-wdt",
311 	{ .compatible = "samsung,s3c6410-wdt",
313 	{ .compatible = "samsung,exynos5250-wdt",
315 	{ .compatible = "samsung,exynos5420-wdt",
317 	{ .compatible = "samsung,exynos7-wdt",
319 	{ .compatible = "samsung,exynos850-wdt",
321 	{ .compatible = "samsung,exynosautov9-wdt",
330 		.name = "s3c2410-wdt",
339 static inline unsigned long s3c2410wdt_get_freq(struct s3c2410_wdt *wdt)
341 	return clk_get_rate(wdt->src_clk ? wdt->src_clk : wdt->bus_clk);
344 static inline unsigned int s3c2410wdt_max_timeout(struct s3c2410_wdt *wdt)
346 	const unsigned long freq = s3c2410wdt_get_freq(wdt);
352 static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
354 	const u32 mask_val = BIT(wdt->drv_data->mask_bit);
358 	ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg,
361 		dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
366 static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
368 	const u32 mask_val = BIT(wdt->drv_data->mask_bit);
369 	const bool val_inv = wdt->drv_data->mask_reset_inv;
373 	ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg,
376 		dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
381 static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en)
383 	const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit);
387 	ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg,
390 		dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
395 static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
399 	if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {
400 		ret = s3c2410wdt_disable_wdt_reset(wdt, !en);
405 	if (wdt->drv_data->quirks & QUIRK_HAS_PMU_MASK_RESET) {
406 		ret = s3c2410wdt_mask_wdt_reset(wdt, !en);
411 	if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) {
412 		ret = s3c2410wdt_enable_counter(wdt, en);
421 static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt)
425 	if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
428 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
430 	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
435 	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
438 	spin_lock_irqsave(&wdt->lock, flags);
439 	writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
440 	spin_unlock_irqrestore(&wdt->lock, flags);
445 static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
449 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
451 	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
456 	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
459 	spin_lock_irqsave(&wdt->lock, flags);
460 	__s3c2410wdt_stop(wdt);
461 	spin_unlock_irqrestore(&wdt->lock, flags);
469 	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
472 	spin_lock_irqsave(&wdt->lock, flags);
474 	__s3c2410wdt_stop(wdt);
476 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
487 	dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
488 		wdt->count, wtcon);
490 	writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
491 	writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
492 	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
493 	spin_unlock_irqrestore(&wdt->lock, flags);
501 	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
502 	unsigned long freq = s3c2410wdt_get_freq(wdt);
513 	dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
525 			dev_err(wdt->dev, "timeout %d too big\n", timeout);
530 	dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
534 	wdt->count = count;
537 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
541 	writel(count, wdt->reg_base + S3C2410_WTDAT);
542 	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
552 	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
553 	void __iomem *wdt_base = wdt->reg_base;
600 	struct s3c2410_wdt *wdt = platform_get_drvdata(param);
602 	dev_info(wdt->dev, "watchdog timer expired (irq)\n");
604 	s3c2410wdt_keepalive(&wdt->wdt_device);
606 	if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
607 		writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
612 static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
617 	if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_RST_STAT))
620 	ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
622 		dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
623 	else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
630 s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
672 	wdt->drv_data = variant;
684 	struct s3c2410_wdt *wdt;
689 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
690 	if (!wdt)
693 	wdt->dev = dev;
694 	spin_lock_init(&wdt->lock);
695 	wdt->wdt_device = s3c2410_wdd;
697 	ret = s3c2410_get_wdt_drv_data(pdev, wdt);
701 	if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
702 		wdt->pmureg = exynos_get_pmu_regmap_by_phandle(dev->of_node,
704 		if (IS_ERR(wdt->pmureg))
705 			return dev_err_probe(dev, PTR_ERR(wdt->pmureg),
714 	wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
715 	if (IS_ERR(wdt->reg_base))
716 		return PTR_ERR(wdt->reg_base);
718 	wdt->bus_clk = devm_clk_get_enabled(dev, "watchdog");
719 	if (IS_ERR(wdt->bus_clk))
720 		return dev_err_probe(dev, PTR_ERR(wdt->bus_clk), "failed to get bus clock\n");
726 	wdt->src_clk = devm_clk_get_optional_enabled(dev, "watchdog_src");
727 	if (IS_ERR(wdt->src_clk))
728 		return dev_err_probe(dev, PTR_ERR(wdt->src_clk), "failed to get source clock\n");
730 	wdt->wdt_device.min_timeout = 1;
731 	wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt);
733 	watchdog_set_drvdata(&wdt->wdt_device, wdt);
738 	watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
739 	ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
740 					wdt->wdt_device.timeout);
742 		ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
756 	watchdog_set_nowayout(&wdt->wdt_device, nowayout);
757 	watchdog_set_restart_priority(&wdt->wdt_device, 128);
759 	wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
760 	wdt->wdt_device.parent = dev;
762 	s3c2410wdt_mask_dbgack(wdt);
773 		s3c2410wdt_start(&wdt->wdt_device);
774 		set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
776 		s3c2410wdt_stop(&wdt->wdt_device);
779 	ret = devm_watchdog_register_device(dev, &wdt->wdt_device);
783 	ret = s3c2410wdt_enable(wdt, true);
787 	ret = devm_add_action_or_reset(dev, s3c2410wdt_wdt_disable_action, wdt);
791 	platform_set_drvdata(pdev, wdt);
795 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
807 	struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
809 	s3c2410wdt_enable(wdt, false);
810 	s3c2410wdt_stop(&wdt->wdt_device);
816 	struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
819 	wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
820 	wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
822 	ret = s3c2410wdt_enable(wdt, false);
827 	s3c2410wdt_stop(&wdt->wdt_device);
835 	struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
838 	writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
839 	writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
840 	writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
842 	ret = s3c2410wdt_enable(wdt, true);
847 		(wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
860 		.name	= "s3c2410-wdt",