Lines Matching refs:wdt

59 static inline u32 keembay_wdt_readl(struct keembay_wdt *wdt, u32 offset)
61 return readl(wdt->base + offset);
64 static inline void keembay_wdt_writel(struct keembay_wdt *wdt, u32 offset, u32 val)
66 writel(WDT_UNLOCK, wdt->base + TIM_SAFE);
67 writel(val, wdt->base + offset);
72 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
74 keembay_wdt_writel(wdt, TIM_WATCHDOG, wdog->timeout * wdt->rate);
79 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
85 keembay_wdt_writel(wdt, TIM_WATCHDOG_INT_THRES, th_val * wdt->rate);
90 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
92 keembay_wdt_writel(wdt, TIM_WDOG_EN, WDT_ENABLE);
99 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
101 keembay_wdt_writel(wdt, TIM_WDOG_EN, WDT_DISABLE);
135 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
137 return keembay_wdt_readl(wdt, TIM_WATCHDOG) / wdt->rate;
146 struct keembay_wdt *wdt = dev_id;
150 dev_crit(wdt->wdd.parent, "Intel Keem Bay non-secure wdt timeout.\n");
158 struct keembay_wdt *wdt = dev_id;
161 keembay_wdt_set_pretimeout(&wdt->wdd, 0x0);
164 dev_crit(wdt->wdd.parent, "Intel Keem Bay non-secure wdt pre-timeout.\n");
165 watchdog_notify_pretimeout(&wdt->wdd);
191 struct keembay_wdt *wdt;
194 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
195 if (!wdt)
198 wdt->base = devm_platform_ioremap_resource(pdev, 0);
199 if (IS_ERR(wdt->base))
200 return PTR_ERR(wdt->base);
203 wdt->clk = devm_clk_get(dev, NULL);
204 if (IS_ERR(wdt->clk))
205 return dev_err_probe(dev, PTR_ERR(wdt->clk), "Failed to get clock\n");
207 wdt->rate = clk_get_rate(wdt->clk);
208 if (!wdt->rate)
211 wdt->th_irq = platform_get_irq_byname(pdev, "threshold");
212 if (wdt->th_irq < 0)
213 return dev_err_probe(dev, wdt->th_irq, "Failed to get IRQ for threshold\n");
215 ret = devm_request_irq(dev, wdt->th_irq, keembay_wdt_th_isr, 0,
216 "keembay-wdt", wdt);
220 wdt->to_irq = platform_get_irq_byname(pdev, "timeout");
221 if (wdt->to_irq < 0)
222 return dev_err_probe(dev, wdt->to_irq, "Failed to get IRQ for timeout\n");
224 ret = devm_request_irq(dev, wdt->to_irq, keembay_wdt_to_isr, 0,
225 "keembay-wdt", wdt);
229 wdt->wdd.parent = dev;
230 wdt->wdd.info = &keembay_wdt_info;
231 wdt->wdd.ops = &keembay_wdt_ops;
232 wdt->wdd.min_timeout = WDT_LOAD_MIN;
233 wdt->wdd.max_timeout = WDT_LOAD_MAX / wdt->rate;
234 wdt->wdd.timeout = WDT_TIMEOUT;
235 wdt->wdd.pretimeout = WDT_PRETIMEOUT;
237 watchdog_set_drvdata(&wdt->wdd, wdt);
238 watchdog_set_nowayout(&wdt->wdd, nowayout);
239 watchdog_init_timeout(&wdt->wdd, timeout, dev);
240 keembay_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
241 keembay_wdt_set_pretimeout(&wdt->wdd, wdt->wdd.pretimeout);
243 ret = devm_watchdog_register_device(dev, &wdt->wdd);
247 platform_set_drvdata(pdev, wdt);
249 wdt->wdd.timeout, nowayout ? ", nowayout" : "");
256 struct keembay_wdt *wdt = dev_get_drvdata(dev);
258 if (watchdog_active(&wdt->wdd))
259 return keembay_wdt_stop(&wdt->wdd);
266 struct keembay_wdt *wdt = dev_get_drvdata(dev);
268 if (watchdog_active(&wdt->wdd))
269 return keembay_wdt_start(&wdt->wdd);
278 { .compatible = "intel,keembay-wdt" },