Lines Matching refs:wdt

57 	{ .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
58 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
59 { .compatible = "aspeed,ast2600-wdt", .data = &ast2600_config },
129 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
131 wdt->ctrl |= WDT_CTRL_ENABLE;
133 writel(0, wdt->base + WDT_CTRL);
134 writel(count, wdt->base + WDT_RELOAD_VALUE);
135 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
136 writel(wdt->ctrl, wdt->base + WDT_CTRL);
141 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
143 aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
150 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
152 wdt->ctrl &= ~WDT_CTRL_ENABLE;
153 writel(wdt->ctrl, wdt->base + WDT_CTRL);
160 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
162 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
170 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
177 writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
178 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
186 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
188 u32 s = wdt->cfg->irq_shift;
189 u32 m = wdt->cfg->irq_mask;
192 wdt->ctrl &= ~m;
194 wdt->ctrl |= ((actual << s) & m) | WDT_CTRL_WDT_INTR;
196 wdt->ctrl &= ~WDT_CTRL_WDT_INTR;
198 writel(wdt->ctrl, wdt->base + WDT_CTRL);
206 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
208 wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
209 aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
220 struct aspeed_wdt *wdt = dev_get_drvdata(dev);
221 u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
231 struct aspeed_wdt *wdt = dev_get_drvdata(dev);
239 wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
298 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
299 u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
311 struct aspeed_wdt *wdt;
318 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
319 if (!wdt)
327 wdt->cfg = ofdid->data;
329 wdt->base = devm_platform_ioremap_resource(pdev, 0);
330 if (IS_ERR(wdt->base))
331 return PTR_ERR(wdt->base);
333 wdt->wdd.info = &aspeed_wdt_info;
335 if (wdt->cfg->irq_mask) {
341 wdt);
345 wdt->wdd.info = &aspeed_wdt_pretimeout_info;
349 wdt->wdd.ops = &aspeed_wdt_ops;
350 wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
351 wdt->wdd.parent = dev;
353 wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
354 watchdog_init_timeout(&wdt->wdd, 0, dev);
356 watchdog_set_nowayout(&wdt->wdd, nowayout);
360 * - ast2400 wdt can run at PCLK, or 1MHz
366 if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
367 wdt->ctrl = WDT_CTRL_1MHZ_CLK;
375 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
378 wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
381 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
384 wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
390 wdt->ctrl |= WDT_CTRL_WDT_EXT;
392 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
394 if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
397 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
401 aspeed_wdt_start(&wdt->wdd);
402 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
405 if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
406 (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
408 size_t nrstmask = of_device_is_compatible(np, "aspeed,ast2600-wdt") ? 2 : 1;
409 u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
411 reg &= wdt->cfg->ext_pulse_width_mask;
417 writel(reg, wdt->base + WDT_RESET_WIDTH);
419 reg &= wdt->cfg->ext_pulse_width_mask;
425 writel(reg, wdt->base + WDT_RESET_WIDTH);
429 writel(reset_mask[0], wdt->base + WDT_RESET_MASK1);
431 writel(reset_mask[1], wdt->base + WDT_RESET_MASK2);
436 u32 max_duration = wdt->cfg->ext_pulse_width_mask + 1;
458 writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
461 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
463 wdt->wdd.bootstatus = WDIOF_CARDRESET;
465 if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
466 of_device_is_compatible(np, "aspeed,ast2500-wdt"))
467 wdt->wdd.groups = bswitch_groups;
470 dev_set_drvdata(dev, wdt);
472 return devm_watchdog_register_device(dev, &wdt->wdd);