w1/masters/omap_hdq.c

48 struct hdq_data {
62 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
64 	return __raw_readl(hdq_data->hdq_base + offset);
67 static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
69 	__raw_writel(val, hdq_data->hdq_base + offset);
72 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
75 	u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask)
77 	__raw_writel(new_val, hdq_data->hdq_base + offset);
88 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
96 		while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
104 		while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
117 static u8 hdq_reset_irqstatus(struct hdq_data *hdq_data, u8 bits)
122 	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
123 	status = hdq_data->hdq_irqstatus;
125 	hdq_data->hdq_irqstatus &= ~bits;
126 	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
132 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
137 	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
143 	if (hdq_data->hdq_irqstatus)
144 		dev_err(hdq_data->dev, "TX irqstatus not cleared (%02x)\n",
145 			hdq_data->hdq_irqstatus);
149 	hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
152 	hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
156 		(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TXCOMPLETE),
158 	*status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE);
160 		dev_dbg(hdq_data->dev, "TX wait elapsed\n");
167 		dev_dbg(hdq_data->dev, "timeout waiting for"
174 	ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
178 		dev_dbg(hdq_data->dev, "timeout waiting GO bit"
183 	mutex_unlock(&hdq_data->hdq_mutex);
191 	struct hdq_data *hdq_data = _hdq;
194 	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
195 	hdq_data->hdq_irqstatus |= hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
196 	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
197 	dev_dbg(hdq_data->dev, "hdq_isr: %x\n", hdq_data->hdq_irqstatus);
199 	if (hdq_data->hdq_irqstatus &
232 static int omap_hdq_break(struct hdq_data *hdq_data)
237 	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
239 		dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
244 	if (hdq_data->hdq_irqstatus)
245 		dev_err(hdq_data->dev, "break irqstatus not cleared (%02x)\n",
246 			hdq_data->hdq_irqstatus);
249 	hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
256 		(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TIMEOUT),
258 	tmp_status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TIMEOUT);
260 		dev_dbg(hdq_data->dev, "break wait elapsed\n");
267 		dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x\n",
277 	if (!(hdq_reg_in(hdq_data, OMAP_HDQ_CTRL_STATUS) &
279 		dev_dbg(hdq_data->dev, "Presence bit not set\n");
288 	ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
293 		dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
297 	mutex_unlock(&hdq_data->hdq_mutex);
302 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
307 	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
313 	if (pm_runtime_suspended(hdq_data->dev)) {
318 	if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
319 		hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
326 				   (hdq_data->hdq_irqstatus
330 		status = hdq_reset_irqstatus(hdq_data,
333 		hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
338 			dev_dbg(hdq_data->dev, "timeout waiting for"
344 		hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
347 	*val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
349 	mutex_unlock(&hdq_data->hdq_mutex);
364 	struct hdq_data *hdq_data = _hdq;
369 	err = pm_runtime_get_sync(hdq_data->dev);
371 		pm_runtime_put_noidle(hdq_data->dev);
376 	err = mutex_lock_interruptible(&hdq_data->hdq_mutex);
378 		dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
386 				 (hdq_data->hdq_irqstatus
390 	hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
393 		dev_dbg(hdq_data->dev, "RX wait elapsed\n");
402 				 (hdq_data->hdq_irqstatus
406 	hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
409 		dev_dbg(hdq_data->dev, "RX wait elapsed\n");
431 				 (hdq_data->hdq_irqstatus
435 	hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE);
438 		dev_dbg(hdq_data->dev, "TX wait elapsed\n");
446 	mutex_unlock(&hdq_data->hdq_mutex);
448 	pm_runtime_mark_last_busy(hdq_data->dev);
449 	pm_runtime_put_autosuspend(hdq_data->dev);
457 	struct hdq_data *hdq_data = _hdq;
460 	err = pm_runtime_get_sync(hdq_data->dev);
462 		pm_runtime_put_noidle(hdq_data->dev);
467 	omap_hdq_break(hdq_data);
469 	pm_runtime_mark_last_busy(hdq_data->dev);
470 	pm_runtime_put_autosuspend(hdq_data->dev);
478 	struct hdq_data *hdq_data = _hdq;
482 	ret = pm_runtime_get_sync(hdq_data->dev);
484 		pm_runtime_put_noidle(hdq_data->dev);
489 	ret = hdq_read_byte(hdq_data, &val);
493 	pm_runtime_mark_last_busy(hdq_data->dev);
494 	pm_runtime_put_autosuspend(hdq_data->dev);
502 	struct hdq_data *hdq_data = _hdq;
506 	ret = pm_runtime_get_sync(hdq_data->dev);
508 		pm_runtime_put_noidle(hdq_data->dev);
519 		omap_hdq_break(hdq_data);
521 	ret = hdq_write_byte(hdq_data, byte, &status);
523 		dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
528 	pm_runtime_mark_last_busy(hdq_data->dev);
529 	pm_runtime_put_autosuspend(hdq_data->dev);
540 	struct hdq_data *hdq_data = dev_get_drvdata(dev);
542 	hdq_reg_out(hdq_data, 0, hdq_data->mode);
543 	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
550 	struct hdq_data *hdq_data = dev_get_drvdata(dev);
553 	hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
556 		    hdq_data->mode);
557 	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
570 	struct hdq_data *hdq_data;
575 	hdq_data = devm_kzalloc(dev, sizeof(*hdq_data), GFP_KERNEL);
576 	if (!hdq_data)
579 	hdq_data->dev = dev;
580 	platform_set_drvdata(pdev, hdq_data);
582 	hdq_data->hdq_base = devm_platform_ioremap_resource(pdev, 0);
583 	if (IS_ERR(hdq_data->hdq_base))
584 		return PTR_ERR(hdq_data->hdq_base);
586 	mutex_init(&hdq_data->hdq_mutex);
590 		hdq_data->mode = 0;
593 		hdq_data->mode = 1;
607 	rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
611 	spin_lock_init(&hdq_data->hdq_spinlock);
620 	ret = devm_request_irq(dev, irq, hdq_isr, 0, "omap_hdq", hdq_data);
626 	omap_hdq_break(hdq_data);
631 	omap_w1_master.data = hdq_data;