fbdev/via/via_modesetting.c

20 	struct via_display_timing raw;
22 	raw.hor_total = timing->hor_total / 8 - 5;
23 	raw.hor_addr = timing->hor_addr / 8 - 1;
24 	raw.hor_blank_start = timing->hor_blank_start / 8 - 1;
25 	raw.hor_blank_end = timing->hor_blank_end / 8 - 1;
26 	raw.hor_sync_start = timing->hor_sync_start / 8;
27 	raw.hor_sync_end = timing->hor_sync_end / 8;
28 	raw.ver_total = timing->ver_total - 2;
29 	raw.ver_addr = timing->ver_addr - 1;
30 	raw.ver_blank_start = timing->ver_blank_start - 1;
31 	raw.ver_blank_end = timing->ver_blank_end - 1;
32 	raw.ver_sync_start = timing->ver_sync_start - 1;
33 	raw.ver_sync_end = timing->ver_sync_end - 1;
38 	via_write_reg(VIACR, 0x00, raw.hor_total & 0xFF);
39 	via_write_reg(VIACR, 0x01, raw.hor_addr & 0xFF);
40 	via_write_reg(VIACR, 0x02, raw.hor_blank_start & 0xFF);
41 	via_write_reg_mask(VIACR, 0x03, raw.hor_blank_end & 0x1F, 0x1F);
42 	via_write_reg(VIACR, 0x04, raw.hor_sync_start & 0xFF);
43 	via_write_reg_mask(VIACR, 0x05, (raw.hor_sync_end & 0x1F)
44 		| (raw.hor_blank_end << (7 - 5) & 0x80), 0x9F);
45 	via_write_reg(VIACR, 0x06, raw.ver_total & 0xFF);
46 	via_write_reg_mask(VIACR, 0x07, (raw.ver_total >> 8 & 0x01)
47 		| (raw.ver_addr >> (8 - 1) & 0x02)
48 		| (raw.ver_sync_start >> (8 - 2) & 0x04)
49 		| (raw.ver_blank_start >> (8 - 3) & 0x08)
50 		| (raw.ver_total >> (9 - 5) & 0x20)
51 		| (raw.ver_addr >> (9 - 6) & 0x40)
52 		| (raw.ver_sync_start >> (9 - 7) & 0x80), 0xEF);
53 	via_write_reg_mask(VIACR, 0x09, raw.ver_blank_start >> (9 - 5) & 0x20,
55 	via_write_reg(VIACR, 0x10, raw.ver_sync_start & 0xFF);
56 	via_write_reg_mask(VIACR, 0x11, raw.ver_sync_end & 0x0F, 0x0F);
57 	via_write_reg(VIACR, 0x12, raw.ver_addr & 0xFF);
58 	via_write_reg(VIACR, 0x15, raw.ver_blank_start & 0xFF);
59 	via_write_reg(VIACR, 0x16, raw.ver_blank_end & 0xFF);
60 	via_write_reg_mask(VIACR, 0x33, (raw.hor_sync_start >> (8 - 4) & 0x10)
61 		| (raw.hor_blank_end >> (6 - 5) & 0x20), 0x30);
62 	via_write_reg_mask(VIACR, 0x35, (raw.ver_total >> 10 & 0x01)
63 		| (raw.ver_sync_start >> (10 - 1) & 0x02)
64 		| (raw.ver_addr >> (10 - 2) & 0x04)
65 		| (raw.ver_blank_start >> (10 - 3) & 0x08), 0x0F);
66 	via_write_reg_mask(VIACR, 0x36, raw.hor_total >> (8 - 3) & 0x08, 0x08);
78 	struct via_display_timing raw;
80 	raw.hor_total = timing->hor_total - 1;
81 	raw.hor_addr = timing->hor_addr - 1;
82 	raw.hor_blank_start = timing->hor_blank_start - 1;
83 	raw.hor_blank_end = timing->hor_blank_end - 1;
84 	raw.hor_sync_start = timing->hor_sync_start - 1;
85 	raw.hor_sync_end = timing->hor_sync_end - 1;
86 	raw.ver_total = timing->ver_total - 1;
87 	raw.ver_addr = timing->ver_addr - 1;
88 	raw.ver_blank_start = timing->ver_blank_start - 1;
89 	raw.ver_blank_end = timing->ver_blank_end - 1;
90 	raw.ver_sync_start = timing->ver_sync_start - 1;
91 	raw.ver_sync_end = timing->ver_sync_end - 1;
93 	via_write_reg(VIACR, 0x50, raw.hor_total & 0xFF);
94 	via_write_reg(VIACR, 0x51, raw.hor_addr & 0xFF);
95 	via_write_reg(VIACR, 0x52, raw.hor_blank_start & 0xFF);
96 	via_write_reg(VIACR, 0x53, raw.hor_blank_end & 0xFF);
97 	via_write_reg(VIACR, 0x54, (raw.hor_blank_start >> 8 & 0x07)
98 		| (raw.hor_blank_end >> (8 - 3) & 0x38)
99 		| (raw.hor_sync_start >> (8 - 6) & 0xC0));
100 	via_write_reg_mask(VIACR, 0x55, (raw.hor_total >> 8 & 0x0F)
101 		| (raw.hor_addr >> (8 - 4) & 0x70), 0x7F);
102 	via_write_reg(VIACR, 0x56, raw.hor_sync_start & 0xFF);
103 	via_write_reg(VIACR, 0x57, raw.hor_sync_end & 0xFF);
104 	via_write_reg(VIACR, 0x58, raw.ver_total & 0xFF);
105 	via_write_reg(VIACR, 0x59, raw.ver_addr & 0xFF);
106 	via_write_reg(VIACR, 0x5A, raw.ver_blank_start & 0xFF);
107 	via_write_reg(VIACR, 0x5B, raw.ver_blank_end & 0xFF);
108 	via_write_reg(VIACR, 0x5C, (raw.ver_blank_start >> 8 & 0x07)
109 		| (raw.ver_blank_end >> (8 - 3) & 0x38)
110 		| (raw.hor_sync_end >> (8 - 6) & 0x40)
111 		| (raw.hor_sync_start >> (10 - 7) & 0x80));
112 	via_write_reg(VIACR, 0x5D, (raw.ver_total >> 8 & 0x07)
113 		| (raw.ver_addr >> (8 - 3) & 0x38)
114 		| (raw.hor_blank_end >> (11 - 6) & 0x40)
115 		| (raw.hor_sync_start >> (11 - 7) & 0x80));
116 	via_write_reg(VIACR, 0x5E, raw.ver_sync_start & 0xFF);
117 	via_write_reg(VIACR, 0x5F, (raw.ver_sync_end & 0x1F)
118 		| (raw.ver_sync_start >> (8 - 5) & 0xE0));