omapfb/dss/hdmi_wp.c

21 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
45 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
47 	return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
50 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
52 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
54 	hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
57 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
59 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
62 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
64 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
68 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
71 	if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
75 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);
78 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
88 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
91 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);
94 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
103 int hdmi_wp_video_start(struct hdmi_wp_data *wp)
105 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);
110 void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
114 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);
116 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);
123 		v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
131 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
136 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
141 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
144 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
154 	r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
159 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
162 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
173 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
178 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
203 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
210 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
223 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
226 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
233 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
236 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);
238 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
241 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
244 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
246 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);
251 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
253 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
258 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)
262 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");
267 	wp->phys_base = res->start;
269 	wp->base = devm_ioremap_resource(&pdev->dev, res);
270 	if (IS_ERR(wp->base)) {
272 		return PTR_ERR(wp->base);
278 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
280 	return wp->phys_base + HDMI_WP_AUDIO_DATA;