Lines Matching refs:fck
514 unsigned long fck;
527 fck = pck * pckd;
529 fck = clk_round_rate(dss.dss_clk, fck);
531 return func(fck, data);
545 fck = DIV_ROUND_UP(prate, fckd) * m;
547 if (func(fck, data))
558 DSSDBG("set fck to %lu\n", rate);
581 unsigned long fck;
588 fck = clk_round_rate(dss.dss_clk, max_dss_fck);
594 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
597 r = dss_set_fck_rate(fck);
735 clk = devm_clk_get(&dss.pdev->dev, "fck");
737 DSSERR("can't get clock fck\n");
816 * fck div max is really 16, but the divider range has gaps. The range