Lines Matching defs:minfo
37 static void DAC1064_calcclock(const struct matrox_fb_info *minfo,
49 fvco = PLL_calcclock(minfo, freq, fmax, in, feed, &p);
88 static void DAC1064_setpclk(struct matrox_fb_info *minfo, unsigned long fout)
94 DAC1064_calcclock(minfo, fout, minfo->max_pixel_clock, &m, &n, &p);
95 minfo->hw.DACclk[0] = m;
96 minfo->hw.DACclk[1] = n;
97 minfo->hw.DACclk[2] = p;
100 static void DAC1064_setmclk(struct matrox_fb_info *minfo, int oscinfo,
104 struct matrox_hw_state *hw = &minfo->hw;
108 if (minfo->devflags.noinit) {
110 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
111 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
112 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
116 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
131 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
133 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
142 DAC1064_calcclock(minfo, fmem, minfo->max_pixel_clock, &m, &n, &p);
143 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3] = m);
144 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4] = n);
145 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5] = p);
147 if (inDAC1064(minfo, DAC1064_XSYSPLLSTAT) & 0x40)
158 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
160 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
165 static void g450_set_plls(struct matrox_fb_info *minfo)
169 struct matrox_hw_state *hw = &minfo->hw;
176 pixelmnp = minfo->crtc1.mnp;
177 videomnp = minfo->crtc2.mnp;
181 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) {
196 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
197 matroxfb_g450_setpll_cond(minfo, videomnp, M_VIDEO_PLL);
204 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
205 matroxfb_g450_setpll_cond(minfo, pixelmnp, M_PIXEL_PLL_C);
212 pxc = minfo->crtc1.pixclock;
213 if (pxc == 0 || minfo->outputs[2].src == MATROXFB_SRC_CRTC2) {
214 pxc = minfo->crtc2.pixclock;
216 if (minfo->chip == MGA_G550) {
257 void DAC1064_global_init(struct matrox_fb_info *minfo)
259 struct matrox_hw_state *hw = &minfo->hw;
265 if (minfo->devflags.g450dac) {
269 switch (minfo->outputs[0].src) {
278 switch (minfo->outputs[1].src) {
283 if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_MONITOR) {
293 switch (minfo->outputs[2].src) {
312 g450_set_plls(minfo);
316 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) {
319 } else if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) {
321 } else if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1)
326 if (minfo->outputs[0].src != MATROXFB_SRC_NONE)
331 void DAC1064_global_restore(struct matrox_fb_info *minfo)
333 struct matrox_hw_state *hw = &minfo->hw;
335 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
336 outDAC1064(minfo, M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]);
337 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) {
338 outDAC1064(minfo, 0x20, 0x04);
339 outDAC1064(minfo, 0x1F, minfo->devflags.dfp_type);
340 if (minfo->devflags.g450dac) {
341 outDAC1064(minfo, M1064_XSYNCCTRL, 0xCC);
342 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
343 outDAC1064(minfo, M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]);
344 outDAC1064(minfo, M1064_XOUTPUTCONN, hw->DACreg[POS1064_XOUTPUTCONN]);
349 static int DAC1064_init_1(struct matrox_fb_info *minfo, struct my_timming *m)
351 struct matrox_hw_state *hw = &minfo->hw;
356 switch (minfo->fbcon.var.bits_per_pixel) {
362 if (minfo->fbcon.var.green.length == 5)
376 hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl;
382 DAC1064_global_init(minfo);
386 static int DAC1064_init_2(struct matrox_fb_info *minfo, struct my_timming *m)
388 struct matrox_hw_state *hw = &minfo->hw;
392 if (minfo->fbcon.var.bits_per_pixel > 16) { /* 256 entries */
400 } else if (minfo->fbcon.var.bits_per_pixel > 8) {
401 if (minfo->fbcon.var.green.length == 5) { /* 0..31, 128..159 */
429 static void DAC1064_restore_1(struct matrox_fb_info *minfo)
431 struct matrox_hw_state *hw = &minfo->hw;
439 if ((inDAC1064(minfo, DAC1064_XSYSPLLM) != hw->DACclk[3]) ||
440 (inDAC1064(minfo, DAC1064_XSYSPLLN) != hw->DACclk[4]) ||
441 (inDAC1064(minfo, DAC1064_XSYSPLLP) != hw->DACclk[5])) {
442 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3]);
443 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4]);
444 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5]);
451 outDAC1064(minfo, MGA1064_DAC_regs[i], hw->DACreg[i]);
455 DAC1064_global_restore(minfo);
460 static void DAC1064_restore_2(struct matrox_fb_info *minfo)
471 dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]);
476 dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]);
482 #define minfo ((struct matrox_fb_info*)out)
488 DAC1064_setpclk(minfo, m->pixclock);
493 outDAC1064(minfo, M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]);
495 if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40)
505 #undef minfo
516 #define minfo ((struct matrox_fb_info*)out)
518 m->mnp = matroxfb_g450_setclk(minfo, m->pixclock, (m->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
520 m->pixclock = g450_mnp2f(minfo, m->mnp);
523 #undef minfo
536 static int MGA1064_init(struct matrox_fb_info *minfo, struct my_timming *m)
538 struct matrox_hw_state *hw = &minfo->hw;
542 if (DAC1064_init_1(minfo, m)) return 1;
543 if (matroxfb_vgaHWinit(minfo, m)) return 1;
553 if (DAC1064_init_2(minfo, m)) return 1;
559 static int MGAG100_init(struct matrox_fb_info *minfo, struct my_timming *m)
561 struct matrox_hw_state *hw = &minfo->hw;
565 if (DAC1064_init_1(minfo, m)) return 1;
567 if (matroxfb_vgaHWinit(minfo, m)) return 1;
577 if (DAC1064_init_2(minfo, m)) return 1;
583 static void MGA1064_ramdac_init(struct matrox_fb_info *minfo)
588 /* minfo->features.DAC1064.vco_freq_min = 120000; */
589 minfo->features.pll.vco_freq_min = 62000;
590 minfo->features.pll.ref_freq = 14318;
591 minfo->features.pll.feed_div_min = 100;
592 minfo->features.pll.feed_div_max = 127;
593 minfo->features.pll.in_div_min = 1;
594 minfo->features.pll.in_div_max = 31;
595 minfo->features.pll.post_shift_max = 3;
596 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_EXTERNAL;
598 DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PLL, 133333);
610 static void MGAG100_progPixClock(const struct matrox_fb_info *minfo, int flags,
619 outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) | M1064_XPIXCLKCTRL_DIS |
626 outDAC1064(minfo, reg++, m);
627 outDAC1064(minfo, reg++, n);
628 outDAC1064(minfo, reg, p);
640 if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40)
646 selClk = inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_SRC_MASK;
652 outDAC1064(minfo, M1064_XPIXCLKCTRL, selClk);
653 outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_DIS);
656 static void MGAG100_setPixClock(const struct matrox_fb_info *minfo, int flags,
663 DAC1064_calcclock(minfo, freq, minfo->max_pixel_clock, &m, &n, &p);
664 MGAG100_progPixClock(minfo, flags, m, n, p);
669 static int MGA1064_preinit(struct matrox_fb_info *minfo)
674 struct matrox_hw_state *hw = &minfo->hw;
678 /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */
679 minfo->capable.text = 1;
680 minfo->capable.vxres = vxres_mystique;
682 minfo->outputs[0].output = &m1064;
683 minfo->outputs[0].src = minfo->outputs[0].default_src;
684 minfo->outputs[0].data = minfo;
685 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
687 if (minfo->devflags.noinit)
691 if (minfo->devflags.novga)
693 if (minfo->devflags.nobios)
695 if (minfo->devflags.nopciretry)
697 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
707 static void MGA1064_reset(struct matrox_fb_info *minfo)
712 MGA1064_ramdac_init(minfo);
717 static void g450_mclk_init(struct matrox_fb_info *minfo)
720 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
721 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3 & ~0x00300C03);
722 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
724 if (((minfo->values.reg.opt3 & 0x000003) == 0x000003) ||
725 ((minfo->values.reg.opt3 & 0x000C00) == 0x000C00) ||
726 ((minfo->values.reg.opt3 & 0x300000) == 0x300000)) {
727 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL);
733 pwr = inDAC1064(minfo, M1064_XPWRCTRL) & ~0x02;
734 outDAC1064(minfo, M1064_XPWRCTRL, pwr);
737 matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL);
740 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
741 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3);
742 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
746 static void g450_memory_init(struct matrox_fb_info *minfo)
749 minfo->hw.MXoptionReg &= ~0x001F8000;
750 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
753 minfo->hw.MXoptionReg &= ~0x00207E00;
754 minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt;
755 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
756 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2);
758 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
761 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U);
762 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
763 mga_outl(M_MACCESS, minfo->values.reg.maccess);
765 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U);
769 if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) {
770 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000);
772 mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000);
776 minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt;
777 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
783 if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) {
784 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core);
789 static void g450_preinit(struct matrox_fb_info *minfo)
795 /* minfo->hw.MXoptionReg = minfo->values.reg.opt; */
796 minfo->hw.MXoptionReg &= 0xC0000100;
797 minfo->hw.MXoptionReg |= 0x00000020;
798 if (minfo->devflags.novga)
799 minfo->hw.MXoptionReg &= ~0x00000100;
800 if (minfo->devflags.nobios)
801 minfo->hw.MXoptionReg &= ~0x40000000;
802 if (minfo->devflags.nopciretry)
803 minfo->hw.MXoptionReg |= 0x20000000;
804 minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040;
805 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
813 curctl = inDAC1064(minfo, M1064_XCURCTRL);
814 outDAC1064(minfo, M1064_XCURCTRL, 0);
819 g450_mclk_init(minfo);
820 g450_memory_init(minfo);
823 matroxfb_g450_setclk(minfo, 25175, M_PIXEL_PLL_A);
824 matroxfb_g450_setclk(minfo, 28322, M_PIXEL_PLL_B);
830 outDAC1064(minfo, M1064_XCURCTRL, curctl);
838 static int MGAG100_preinit(struct matrox_fb_info *minfo)
843 struct matrox_hw_state *hw = &minfo->hw;
853 if (minfo->devflags.g450dac) {
854 minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */
856 minfo->features.pll.vco_freq_min = 62000;
858 if (!minfo->features.pll.ref_freq) {
859 minfo->features.pll.ref_freq = 27000;
861 minfo->features.pll.feed_div_min = 7;
862 minfo->features.pll.feed_div_max = 127;
863 minfo->features.pll.in_div_min = 1;
864 minfo->features.pll.in_div_max = 31;
865 minfo->features.pll.post_shift_max = 3;
866 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_G100_DEFAULT;
867 /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */
868 minfo->capable.text = 1;
869 minfo->capable.vxres = vxres_g100;
870 minfo->capable.plnwt = minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100
871 ? minfo->devflags.sgram : 1;
873 if (minfo->devflags.g450dac) {
874 minfo->outputs[0].output = &g450out;
876 minfo->outputs[0].output = &m1064;
878 minfo->outputs[0].src = minfo->outputs[0].default_src;
879 minfo->outputs[0].data = minfo;
880 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
882 if (minfo->devflags.g450dac) {
887 if (minfo->devflags.noinit)
889 if (minfo->devflags.g450dac) {
890 g450_preinit(minfo);
895 if (minfo->devflags.novga)
897 if (minfo->devflags.nobios)
899 if (minfo->devflags.nopciretry)
901 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
902 DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PCI, 133333);
904 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100) {
905 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50);
907 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
910 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
911 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
921 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
927 mga_writeb(minfo->video.vbase, 0x0000, 0xAA);
928 mga_writeb(minfo->video.vbase, 0x0800, 0x55);
929 mga_writeb(minfo->video.vbase, 0x4000, 0x55);
931 if (mga_readb(minfo->video.vbase, 0x0000) != 0xAA) {
936 } else if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG200) {
937 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50);
939 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
941 if (minfo->devflags.memtype == -1)
942 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
944 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
945 if (minfo->devflags.sgram)
947 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
948 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
953 mga_outw(M_MEMRDBK, minfo->values.reg.memrdbk);
956 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50);
959 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
961 if (minfo->devflags.memtype == -1)
962 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
964 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
965 if (minfo->devflags.sgram)
967 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
968 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
973 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
976 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
980 static void MGAG100_reset(struct matrox_fb_info *minfo)
983 struct matrox_hw_state *hw = &minfo->hw;
993 if (b == minfo->pcidev->bus->number) {
1000 if (!minfo->devflags.noinit) {
1003 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1008 if (minfo->devflags.g450dac) {
1010 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
1011 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
1012 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
1014 DAC1064_setmclk(minfo, DAC1064_OPT_RESERVED | DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV1 | DAC1064_OPT_SCLK_PLL, 133333);
1016 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) {
1017 if (minfo->devflags.dfp_type == -1) {
1018 minfo->devflags.dfp_type = inDAC1064(minfo, 0x1F);
1021 if (minfo->devflags.noinit)
1023 if (minfo->devflags.g450dac) {
1025 MGAG100_setPixClock(minfo, 4, 25175);
1026 MGAG100_setPixClock(minfo, 5, 28322);
1028 b = inDAC1064(minfo, M1064_XGENIODATA) & ~1;
1029 outDAC1064(minfo, M1064_XGENIODATA, b);
1030 b = inDAC1064(minfo, M1064_XGENIOCTRL) | 1;
1031 outDAC1064(minfo, M1064_XGENIOCTRL, b);
1038 static void MGA1064_restore(struct matrox_fb_info *minfo)
1041 struct matrox_hw_state *hw = &minfo->hw;
1049 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1055 DAC1064_restore_1(minfo);
1056 matroxfb_vgaHWrestore(minfo);
1057 minfo->crtc1.panpos = -1;
1060 DAC1064_restore_2(minfo);
1065 static void MGAG100_restore(struct matrox_fb_info *minfo)
1068 struct matrox_hw_state *hw = &minfo->hw;
1076 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1079 DAC1064_restore_1(minfo);
1080 matroxfb_vgaHWrestore(minfo);
1081 if (minfo->devflags.support32MB)
1083 minfo->crtc1.panpos = -1;
1086 DAC1064_restore_2(minfo);