Lines Matching refs:regbase
356 u8 __iomem *regbase;
396 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
397 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
402 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
411 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
413 caddr_t regbase,
452 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
639 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
645 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
649 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
651 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
663 u8 __iomem *regbase = cinfo->regbase;
749 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
753 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
756 vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
759 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
763 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
767 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
773 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
776 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
794 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
802 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
805 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
808 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
811 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
814 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
817 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
820 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
835 vga_wcrt(regbase, CL_CRT1A, tmp);
897 vga_wseq(regbase, CL_SEQRE, tmp);
898 vga_wseq(regbase, CL_SEQR1E, nom);
900 vga_wseq(regbase, CL_SEQRE, nom);
901 vga_wseq(regbase, CL_SEQR1E, tmp);
907 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
911 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
916 vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
918 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
930 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
932 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
943 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
954 vga_wseq(regbase, CL_SEQR7,
961 vga_wseq(regbase, CL_SEQR7,
962 vga_rseq(regbase, CL_SEQR7) & ~0x01);
976 vga_wseq(regbase, CL_SEQRF, 0xb0);
981 vga_wseq(regbase, CL_SEQRF, 0xd0);
1007 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1009 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1028 vga_wseq(regbase, CL_SEQR7,
1035 vga_wseq(regbase, CL_SEQR7,
1036 vga_rseq(regbase, CL_SEQR7) | 0x01);
1050 vga_wseq(regbase, CL_SEQRF, 0xb0);
1056 vga_wseq(regbase, CL_SEQRF, 0xb8);
1072 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1092 vga_wseq(regbase, CL_SEQR7, 0x87);
1094 vga_wseq(regbase, CL_SEQRF, 0xb0);
1098 vga_wseq(regbase, CL_SEQR7, 0x27);
1100 vga_wseq(regbase, CL_SEQRF, 0xb0);
1107 vga_wseq(regbase, CL_SEQR7,
1112 vga_wseq(regbase, CL_SEQR7, 0x17);
1118 vga_wseq(regbase, CL_SEQR7,
1119 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1131 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1151 vga_wseq(regbase, CL_SEQR7, 0x85);
1153 vga_wseq(regbase, CL_SEQRF, 0xb0);
1157 vga_wseq(regbase, CL_SEQR7, 0x25);
1159 vga_wseq(regbase, CL_SEQRF, 0xb0);
1166 vga_wseq(regbase, CL_SEQR7, 0xa5);
1170 vga_wseq(regbase, CL_SEQR7, 0x15);
1176 vga_wseq(regbase, CL_SEQR7,
1177 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1189 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1206 vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
1212 vga_wcrt(regbase, CL_CRT1B, tmp);
1216 vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
1233 vga_wcrt(regbase, CL_CRT1E, tmp);
1238 vga_wattr(regbase, CL_AR33, 0);
1259 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1340 cirrusfb_WaitBLT(cinfo->regbase);
1343 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
1344 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
1347 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1356 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1360 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
1365 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
1373 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1412 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1413 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1434 vga_wgfx(cinfo->regbase, CL_GRE, val);
1477 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1480 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1484 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1488 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1517 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1520 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1523 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1525 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1529 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1537 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1541 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1542 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1547 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1549 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1551 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1555 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1557 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1561 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1563 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1565 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1567 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1572 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1574 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1578 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1580 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1582 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1584 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1586 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1589 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1592 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1595 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1597 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1599 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1601 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1603 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1605 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1607 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1609 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1611 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1616 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1621 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1623 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1624 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1625 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1627 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1628 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1644 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1645 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1646 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1649 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1651 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1653 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1655 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1660 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1662 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1725 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
1762 cirrusfb_RectFill(cinfo->regbase,
1803 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1839 cirrusfb_RectFill(cinfo->regbase,
1847 cirrusfb_RectFill(cinfo->regbase,
1865 u8 __iomem *regbase)
1871 unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
1875 unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
1953 iounmap(cinfo->regbase);
2119 cinfo->regbase = NULL;
2126 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2204 unsigned long regbase, ramsize, rambase;
2213 regbase = zorro_resource_start(z) + zcl->regoffset;
2244 cirrusfb_board_info[btype].name, regbase, ramsize / MB_,
2256 info->fix.mmio_start = regbase;
2257 cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024)
2258 : ZTWO_VADDR(regbase);
2259 if (!cinfo->regbase) {
2283 vga_wseq(cinfo->regbase, CL_SEQR1F,
2301 if (regbase > 16 * MB_)
2302 iounmap(cinfo->regbase);
2425 vga_w(cinfo->regbase, regofs + regnum, val);
2441 return vga_r(cinfo->regbase, regofs + regnum);
2449 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2452 vga_w(cinfo->regbase, VGA_ATT_IW,
2453 vga_r(cinfo->regbase, VGA_ATT_R));
2456 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2457 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2460 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2512 assert(cinfo->regbase != NULL);
2514 z_writeb(val, cinfo->regbase + 0x8000);
2524 assert(cinfo->regbase != NULL);
2526 z_writeb(val, cinfo->regbase + 0x9000);
2537 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2545 vga_w(cinfo->regbase, data, red);
2546 vga_w(cinfo->regbase, data, green);
2547 vga_w(cinfo->regbase, data, blue);
2549 vga_w(cinfo->regbase, data, blue);
2550 vga_w(cinfo->regbase, data, green);
2551 vga_w(cinfo->regbase, data, red);
2562 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2568 *red = vga_r(cinfo->regbase, data);
2569 *green = vga_r(cinfo->regbase, data);
2570 *blue = vga_r(cinfo->regbase, data);
2572 *blue = vga_r(cinfo->regbase, data);
2573 *green = vga_r(cinfo->regbase, data);
2574 *red = vga_r(cinfo->regbase, data);
2586 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2588 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2598 static void cirrusfb_set_blitter(u8 __iomem *regbase,
2606 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2608 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2610 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2612 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2616 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2618 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2622 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2624 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2628 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2630 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2632 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2636 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2638 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2640 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2643 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2646 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2649 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2658 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2690 cirrusfb_WaitBLT(regbase);
2692 cirrusfb_set_blitter(regbase, nwidth, nheight,
2702 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2710 cirrusfb_WaitBLT(regbase);
2714 vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
2715 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
2719 vga_wgfx(regbase, CL_GR10, bg_color >> 8);
2720 vga_wgfx(regbase, CL_GR11, fg_color >> 8);
2724 vga_wgfx(regbase, CL_GR12, bg_color >> 16);
2725 vga_wgfx(regbase, CL_GR13, fg_color >> 16);
2729 vga_wgfx(regbase, CL_GR14, bg_color >> 24);
2730 vga_wgfx(regbase, CL_GR15, fg_color >> 24);
2733 cirrusfb_set_blitter(regbase, width - 1, height - 1,
2808 * @regbase: If using newmmio, the newmmio base address, otherwise %NULL
2818 caddr_t regbase,
2834 val = vga_rcrt(regbase, (unsigned char) reg);
2837 val = vga_rseq(regbase, (unsigned char) reg);
2863 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
2867 cirrusfb_dbg_print_regs(info, regbase, CRT,
2921 cirrusfb_dbg_print_regs(info, regbase, SEQ,