fbdev/aty/radeon_base.c

303 		u32 save, tmp;
304 		save = INREG(CLOCK_CNTL_INDEX);
305 		tmp = save & ~(0x3f | PLL_WR_EN);
308 		OUTREG(CLOCK_CNTL_INDEX, save);
1311 			       struct radeon_regs *save)
1314 	save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1315 	save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1316 	save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1317 	save->dac_cntl = INREG(DAC_CNTL);
1318         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1319         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1320         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1321         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1322 	save->crtc_pitch = INREG(CRTC_PITCH);
1323 	save->surface_cntl = INREG(SURFACE_CNTL);
1326 	save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1327 	save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1328 	save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1329 	save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1330 	save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1331 	save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1332 	save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1333 	save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1334 	save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1335 	save->tmds_crc = INREG(TMDS_CRC);
1336 	save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1337 	save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1340 	save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1342 	save->ppll_div_3 = INPLL(PPLL_DIV_3);
1343 	save->ppll_ref_div = INPLL(PPLL_REF_DIV);
2438 	/* save current mode regs before we switch into the new one