vfio/pci/vfio_pci_config.c

113 			  struct perm_bits *perm, int offset, __le32 *val);
115 			   struct perm_bits *perm, int offset, __le32 val);
176 				    int count, struct perm_bits *perm,
183 	memcpy(&virt, perm->virt + offset, count);
202 				     int count, struct perm_bits *perm,
207 	memcpy(&write, perm->write + offset, count);
212 	memcpy(&virt, perm->virt + offset, count);
249 				   int count, struct perm_bits *perm,
274 				 int count, struct perm_bits *perm,
287 				int count, struct perm_bits *perm,
301 				  int count, struct perm_bits *perm,
309 				 int count, struct perm_bits *perm,
339 static void free_perm_bits(struct perm_bits *perm)
341 	kfree(perm->virt);
342 	kfree(perm->write);
343 	perm->virt = NULL;
344 	perm->write = NULL;
347 static int alloc_perm_bits(struct perm_bits *perm, int size)
363 	perm->virt = kzalloc(size, GFP_KERNEL);
364 	perm->write = kzalloc(size, GFP_KERNEL);
365 	if (!perm->virt || !perm->write) {
366 		free_perm_bits(perm);
370 	perm->readfn = vfio_default_config_read;
371 	perm->writefn = vfio_default_config_write;
522 				  int count, struct perm_bits *perm,
528 	count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
560 				   int count, struct perm_bits *perm,
609 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
652 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
654 	if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
657 	perm->readfn = vfio_basic_config_read;
658 	perm->writefn = vfio_basic_config_write;
661 	p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
662 	p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
668 	p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
671 	p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
674 	p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
675 	p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
676 	p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
679 	p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
680 	p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
681 	p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
682 	p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
683 	p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
684 	p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
685 	p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
688 	p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
691 	p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
694 	p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
716 				int count, struct perm_bits *perm,
719 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
748 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
750 	if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
753 	perm->writefn = vfio_pm_config_write;
759 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
768 	p_setw(perm, PCI_PM_PMC, PCI_PM_CAP_PME_MASK, NO_WRITE);
779 	p_setd(perm, PCI_PM_CTRL,
788 				 int count, struct perm_bits *perm,
802 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
832 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
834 	if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
837 	perm->writefn = vfio_vpd_config_write;
843 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
849 	p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
850 	p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
856 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
859 	if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
862 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
864 	p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
865 	p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
870 				 int count, struct perm_bits *perm,
877 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
929 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
932 	if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
935 	perm->writefn = vfio_exp_config_write;
937 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
946 	p_setw(perm, PCI_EXP_DEVCTL,
949 	p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
954 				int count, struct perm_bits *perm,
959 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
990 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
992 	if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
995 	perm->writefn = vfio_af_config_write;
997 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
998 	p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
1003 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
1007 	if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
1015 	p_setd(perm, 0, ALL_VIRT, NO_WRITE);
1035 	p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
1036 	p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
1037 	p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
1047 	p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
1048 	p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
1052 	p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
1057 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
1059 	if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
1062 	p_setd(perm, 0, ALL_VIRT, NO_WRITE);
1065 	p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
1131 				int count, struct perm_bits *perm,
1147 	return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1151 				 int count, struct perm_bits *perm,
1154 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1196 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1198 	if (alloc_perm_bits(perm, len))
1201 	perm->readfn = vfio_msi_config_read;
1202 	perm->writefn = vfio_msi_config_write;
1204 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1210 	p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1211 	p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1213 		p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1214 		p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1216 			p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1217 			p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1220 		p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1222 			p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1223 			p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1866 	struct perm_bits *perm;
1893 		perm = &unassigned_perms;
1896 		perm = &virt_perms;
1902 			perm = &ecap_perms[cap_id];
1907 			perm = &cap_perms[cap_id];
1910 				perm = vdev->msi_perm;
1923 		if (!perm->writefn)
1929 		ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1931 		if (perm->readfn) {
1932 			ret = perm->readfn(vdev, *ppos, count,
1933 					   perm, offset, &val);